Ahhh, thanks.
Is that different from the fc5 rpm right under it? I grabbed that and
installed it, no problems, but no new components either after a gschem
restart. I don't see a place in gschemrc to spec the new 'smallsym'
directory as a path to search for symbols. I could
On Mon, 15 Oct 2007 00:14:24 +0200, Stefan Salewski wrote:
Can we compress this in one single command Save Symbol as...?
Ack. I always feel like a bash script when I go through these steps.
Did you consider to file a feature request?
---(kaimartin)---
--
Kai-Martin Knaak
Levente wrote:
I think the padstacks should be defined elsewhere, and we should only have a
reference for it in the PCB file. Same goes for pads in padstack. So I prefer
light footprints. Just my EUR 0.02.
Could a file-wide pad stack handle all cases of using a padstack? I am thinking
John Griessen wrote:
Could a file-wide pad stack handle all cases of using a padstack? I
am thinking
Dave wants to vary the shape of paste layer from place to place...
What I want is simple. For any footprint, it needs to draw a paste
layer that cuts a reliable stencil. I don't need to
Gschem's primary purpose is schematic capture. If what you want is
publication quality schematic drawings use XCircuit.
http://opencircuitdesign.com/xcircuit/.
What would be really nice would be a translator between the two
___
geda-user mailing list
On Monday 15 October 2007 17:27:43 Chris Albertson wrote:
Gschem's primary purpose is schematic capture. If what you want is
publication quality schematic drawings use XCircuit.
http://opencircuitdesign.com/xcircuit/.
I'm afraid that this is just not true. It's entirely possible to
produce
On Monday 15 October 2007 18:10:05 DJ Delorie wrote:
It got me to thinking - maybe some of us could get together and
collaborate on a design? Each offering their expertise and time,
using a central CVS/SVN server to hold the (yay ascii!) design files.
Hmm, I'd better hurry up and get the
On Oct 15, 2007, at 1:10 PM, DJ Delorie wrote:
I've been following this project: http://www.itredux.com/
At this point, he's looking for someone to design (or at least start
designing) the PCB. I'd offer myself, but he needs RF experience that
I don't yet have (it's got 802.11, CDMA, GSM,
Peter TB Brett wrote:
On Monday 15 October 2007 18:10:05 DJ Delorie wrote:
It got me to thinking - maybe some of us could get together and
collaborate on a design? Each offering their expertise and time,
using a central CVS/SVN server to hold the (yay ascii!) design files.
Hmm, I'd
Take a look at it now; I just re-ran the 3:15 run with the new export
routine.
-Original Message-
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of DJ Delorie
Sent: Monday, October 15, 2007 3:14 PM
To: [EMAIL PROTECTED]
Cc: geda-user@moria.seul.org
Subject: Re:
Ooops, clicked reply to wrong list!
-Original Message-
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of David Kerber
Sent: Monday, October 15, 2007 3:36 PM
To: 'gEDA user mailing list'
Subject: Re: gEDA-user: PCB paste layer, revisited.
Take a look at it now; I
DJ Delorie wrote:
The data structures aren't that hard to understand, it's the code that
manipulates them that's tricky.
While I appreciate knowing that, your comment is 100% content free. It
is a non-clue.
Can't somebody simply say: Go look if file ___ and read ___.? That is
a clue.
It
The data structures you need to update are called __ in file ___.
Look at the code for ___ and use the same architecture to do ___.
There will be gotchas w.r.t. rotate, undo, and ___, so look at the code
for ___ in ___.
ElementType global.h CreateNewPad CreateNewPaste DRC DRC() find.c
John Griessen [EMAIL PROTECTED] wrote:
Levente wrote:
I think the padstacks should be defined elsewhere, and we should only have a
reference for it in the PCB file. Same goes for pads in padstack. So I prefer
light footprints. Just my EUR 0.02.
Could a file-wide pad stack handle all
Imagine, that you have a 431 pin BGA. Would you include 431 times
the same padstack in the footprint? I think one should bother with
the whatever shape, and size of the stencil, copper, mask, paste
layers. Those are just pads. Then we could link pads to a
padstack, and the padstacks into
DJ Delorie wrote:
It got me to thinking - maybe some of us could get together and
collaborate on a design? Each offering their expertise and time,
using a central CVS/SVN server to hold the (yay ascii!) design files.
It would be a novel way of doing things, and prove some points about
I can contribute on a project that results in a low power ARM9 that
can run linux motherboard.
That sounds like fun too, but I think itredux is calling the shots
about the hardware specs.
At this point, there are two things pending: First, *can* the chips
they choose be used in an open
DJ Delorie wrote:
Imagine, that you have a 431 pin BGA. Would you include 431 times
the same padstack in the footprint? I think one should bother with
the whatever shape, and size of the stencil, copper, mask, paste
layers. Those are just pads. Then we could link pads to a
padstack, and
Just in case any of you gEDA users and developers
come across any other collaboration opps,
open hardware (TAPR license/BSD licenseTinyOS license),
projects on my near future list are:
TinyOS platforms using CC2420 + MSP430F1611,
CC2420 + MSP430F2274
CC2510 alone
contiki platform using
As long as we are on this topic.
the solder mask should be part of the pad stack.
I have some parts/and designs that requite unmasked via's and
shapes. spark gap for extreme over voltage in power supplies.
Not having a true solder mask layer in pcb is a limitation.
overall i see this
Dave N6NZ wrote:
DJ Delorie wrote:
Imagine, that you have a 431 pin BGA. Would you include 431 times
the same padstack in the footprint? I think one should bother with
the whatever shape, and size of the stencil, copper, mask, paste
layers. Those are just pads. Then we could link pads to a
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