Ahmad Sayed wrote:
>>> For example, for a PCI device, the HDL writer will need the test
>>> environment to create PCI cycles (including the clocks) at a *far*
>>> lower level then qemu, for example, provides. Emulating at the BUS
>>> cycle level would drastically slow down a PC emulator.
> PCI dev
I removed the minimum annulus based on copper width check. And for
older .pcb files which don't specify the min annulus, the min width is
used as the default.
Steven Michalske wrote:
> if we open a PCB file that doesn't specify an annulus min width then
> the annulus min width should be set t
Hi John,
>> John Wrote:
>> Is your ultimate target HW/SW design a PC connected to the parallel port
of another custom system board,
>> and thus a fairly low speed, (parallel port speed), design?
>> Is the convenient simulation done with actual software and a
>> iverilog simulation without going th
I've taken the time to finish up the blinker board (second of three
boards) portion of the "Getting Started" doc.
http://www.delorie.com/pcb/docs/gs/
I last left off after creating the custom footprint; the remainder
teaches gsch2pcb and autorouting.
My intention is for the third board to teach
4 matches
Mail list logo
