DJ Delorie wrote:
>> Well, that's enough reason to use the proper grouping. Would
>> 'Optimize Rats' and DRC catch the short, or would it be undetected
>> until you built the board and smoked a part?
>
> In the few cases where I'd seen it, the gerbers are just solid black.
> Really hard to miss.
>
> Well, that's enough reason to use the proper grouping. Would
> 'Optimize Rats' and DRC catch the short, or would it be undetected
> until you built the board and smoked a part?
In the few cases where I'd seen it, the gerbers are just solid black.
Really hard to miss.
More common is polygons on
DJ Delorie wrote:
>> Thanks - I've made that change. Just out of curiosity, what's the
>> impact of the incorrect grouping?
>
> Worst case? Polygons shorting your SMT pads.
Well, that's enough reason to use the proper grouping. Would 'Optimize
Rats' and DRC catch the short, or would it be undet
On Thu, Aug 21, 2008 at 11:32:06PM -0400, DJ Delorie wrote:
>
> > Thanks - I've made that change. Just out of curiosity, what's the
> > impact of the incorrect grouping?
>
> Worst case? Polygons shorting your SMT pads.
Actually I think the true "worst case" is that almost all of the "bad
defaul
> Thanks - I've made that change. Just out of curiosity, what's the
> impact of the incorrect grouping?
Worst case? Polygons shorting your SMT pads.
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DJ Delorie wrote:
>> Interesting. I believe that this grouping came from the default
>> generated by gsch2pcb that 'ships' with the 20080202 rpm from fedora.
>
> In my tutorials, I have the user create a blank board first, then use
> gsch2pcb *only* to add elements and update the netlist.
Aha -
Ben Jackson wrote:
> On Thu, Aug 21, 2008 at 09:45:04PM -0400, DJ Delorie wrote:
>>> http://members.cox.net/ebrombaugh1/synth/dsPICfun2/dsPICfun2.pcb.tgz
>> I've reproduced this, it's the usual b->contours bug.
>
> It is crashing because the polygon dicer is trying to cut a polygon
> through its f
> Interesting. I believe that this grouping came from the default
> generated by gsch2pcb that 'ships' with the 20080202 rpm from fedora.
In my tutorials, I have the user create a blank board first, then use
gsch2pcb *only* to add elements and update the netlist.
> Can I fix it simply by editi
DJ Delorie wrote:
> Quick notes:
>
> One big rectangle is better than five overlapping rectangles.
Indeed - that's what I'd prefer too. My experience with 20080202 however
was that one big rectangle had a tendency to fill incorrectly and leave
large gaps. Multiple overlapping rectangles were my
On Thu, Aug 21, 2008 at 09:45:04PM -0400, DJ Delorie wrote:
>
> > http://members.cox.net/ebrombaugh1/synth/dsPICfun2/dsPICfun2.pcb.tgz
>
> I've reproduced this, it's the usual b->contours bug.
It is crashing because the polygon dicer is trying to cut a polygon
through its first hole, so it const
Quick notes:
One big rectangle is better than five overlapping rectangles.
I don't know how, but you have two groups containing the "component"
side, and two containing the solder side:
Groups("1,2,3,s:4,5,6,c:s:c")
The last :s:c should be :7:8
_
DJ Delorie wrote:
> Yeah, just delete the polygons from the .pcb and it should go away.
> I'll poke at it and see what I can do with it.
That worked. Thanks a bunch!
Eric
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Yeah, just delete the polygons from the .pcb and it should go away.
I'll poke at it and see what I can do with it.
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DJ Delorie wrote:
>> http://members.cox.net/ebrombaugh1/synth/dsPICfun2/dsPICfun2.pcb.tgz
>
> I've reproduced this, it's the usual b->contours bug.
Aha - any way I can hand-edit the .pcb file to recover from this? If
it's just the rectangle fills I wouldn't mind deleting them to get my
routes &
Dan McMahill wrote:
> Eric Brombaugh wrote:
>> the README.cvs document appears to be out of date
>
> I just fixed the README.cvs document to have the right server name.
Thanks!
>> Note that
>> building bombs out on documentation due to lack of some files:
>
> Yep. When building from cvs, you
> http://members.cox.net/ebrombaugh1/synth/dsPICfun2/dsPICfun2.pcb.tgz
I've reproduced this, it's the usual b->contours bug.
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Eric Brombaugh wrote:
> Eric Brombaugh wrote:
>
>> I've been trying to get logged into the sourceforge CVS server
>> for a while now but it seems to be hung (just sits waiting after I hit
>> for the PW prompt). I'll try again later tonight.
>
> That's solved - the README.cvs document appears t
Eric Brombaugh wrote:
> I've been trying to get logged into the sourceforge CVS server
> for a while now but it seems to be hung (just sits waiting after I hit
> for the PW prompt). I'll try again later tonight.
That's solved - the README.cvs document appears to be out of date and is
giving i
Ben Jackson wrote:
> On Thu, Aug 21, 2008 at 05:26:20PM -0700, Eric Brombaugh wrote:
>> I'm using pcb version 20080202 installed from rpm for Fedora 9 with the
>> GTK HID.
>
> As always it's worth trying the CVS, since PCB improvement has been
> rapid in the last year or so.
Thanks - I've been t
On Thu, Aug 21, 2008 at 05:26:20PM -0700, Eric Brombaugh wrote:
>
> I'm using pcb version 20080202 installed from rpm for Fedora 9 with the
> GTK HID.
As always it's worth trying the CVS, since PCB improvement has been
rapid in the last year or so.
You could also make the file available to the
PCB Gurus,
This morning I made some edits to a design, saved the results, quit and
checked them in to CVS. Now when I try to open the design up in PCB the
application bails out without issuing any errors. Running pcb without
arguments brings up the application, but attempting to load the design
Hi everyone,
On the 24th-26th August I'll be off work and spending the time working on some
gEDA things. Specifically:
1. Trawling through the trackers and seeing how many of the issues I can fix.
If there's a small gEDA problem that's bugging you, report it now!
2. Making some minor code chan
If you are planning on printing on toner transfer paper and masking your
copper with that, I believe that the ink jet will not work. If you are
using photo sensitive copper then an ink jet print on transparency will
work, but you will need a negative image of your gerbers.
Eric Winsor
Robert
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