On Wed, 29 Oct 2008 07:53:10 +0200, Duncan Drennan wrote:
I use the attached Makefile for schematic management, and then make
printpdf to create a PDF (currently set to make A4 size pages).
I'd like to add this Makefile to the geda wiki. Would you agree to
publish it under an open source
I'd like to add this Makefile to the geda wiki. Would you agree to
publish it under an open source license (e.g. GPL2)?
Sure!
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On Tue, Oct 28, 2008 at 02:49:37PM -0400, DJ Delorie wrote:
What about high precision ADCs? I'm working on a design using ADE7753
power monitor chips (16-bit ADCs) , and their own app note (AN564)
shows a ferrite isolating analog ground, and a 10R resistor isolating
AVdd.
Newbie questioner...
Is there a way to selectively hide the power pins of a multi-sectioned
component?
That is, without having to resort to the hidden connection (net attribute)
method?
A simple example: a 7400 package, with 4 2-in nand gates. With OrCAD, I was
able
to create a _5_ element
On Fri, Oct 31, 2008 at 2:07 PM, Frank Miles [EMAIL PROTECTED] wrote:
A simple example: a 7400 package, with 4 2-in nand gates. With OrCAD, I was
able
to create a _5_ element device: 4 with the gates (no power connections), and
a 5th
section with power connections only.
I create separate
nice board,
Why did you connect the vias attach to the planes with thermals
instead of a solid thermal connection?
Steve
On Oct 30, 2008, at 10:26 PM, DJ Delorie wrote:
http://www.delorie.com/electronics/powermeter/
I merged the three ground planes into one, and draw AVdd from DVdd for
I have three pages of schematics named: name_1.sch, name_2.sch and
name_3.sch. I want to autonumber the refdeses for the whole
hierarchy. I did a tu, set it for autonumber text in: whole
hierarchy, skip numbers found in: selected objects and I checked the
overwrite existing
On Fri, 31 Oct 2008 14:15:08 -0400, John Luciani wrote:
I create separate power symbols. You just need to give the power symbol
and the gate symbol the same refdes.
... and attach the same footprint attribute to both of them. If you
insist to attach the footprint to only one symbol of the
Why did you connect the vias attach to the planes with thermals
instead of a solid thermal connection?
Because I make my own boards, and have to solder all the vias. I'll
make them solid if I send them out to fab.
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Thanks John and Kai-Martin, that should be an adequate if awkward work-around.
It must also be the approach to take when other shape changes are desirable
beyond the limits of rotation and mirroring.
-Frank
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DJ Delorie wrote:
http://www.delorie.com/electronics/powermeter/
I merged the three ground planes into one, and draw AVdd from DVdd for
each chip, with a 10R/10uF power filter.
There's still a big hole in the ground plane where the Vdd plane
goes, as well as all the digital signals to
Much better. If you want to be extra good provide another 0.1uF
parallel to the AVDD caps, close to pin 3.
The problem is, there's no ground near pin 3. The Vdds are all near
pin 1, and the GNDs are all near pin 10.
Might want to rotate C11 and squeeze it in between R18/C12 so it's
closer
Frank Miles wrote:
Newbie questioner...
Is there a way to selectively hide the power pins of a multi-sectioned
component?
That is, without having to resort to the hidden connection (net attribute)
method?
Create multiple symbols.
A simple example: a 7400 package, with 4 2-in nand
Kai-Martin Knaak wrote:
On Fri, 31 Oct 2008 14:15:08 -0400, John Luciani wrote:
I create separate power symbols. You just need to give the power symbol
and the gate symbol the same refdes.
... and attach the same footprint attribute to both of them. If you
insist to attach the footprint
DJ Delorie wrote:
Much better. If you want to be extra good provide another 0.1uF
parallel to the AVDD caps, close to pin 3.
The problem is, there's no ground near pin 3. The Vdds are all near
pin 1, and the GNDs are all near pin 10.
Isn't that whole outside perimeter plane GND?
I figured a way to do it. I doubt itsright but it worked.
For each page I did an autonumer text and searched for each type of
component. Then I started numbering from the component on the
previous page.
On Fri, Oct 31, 2008 at 2:41 PM, Rob Butts [EMAIL PROTECTED]
wrote:
Isn't that whole outside perimeter plane GND?
Yeah, but I usually try to keep the caps closer to the ground pins as
well as the vdd pins. A lot of the chips I usually deal with (like
the R8C) have the power pins near each other so you can bypass right
at the chip.
Nope. It's inside a metal
DJ Delorie wrote:
Isn't that whole outside perimeter plane GND?
Yeah, but I usually try to keep the caps closer to the ground pins as
well as the vdd pins. A lot of the chips I usually deal with (like
the R8C) have the power pins near each other so you can bypass right
at the chip.
It's
On Friday 31 October 2008 20:22:59 Joerg wrote:
Might want to rotate C11 and squeeze it in between R18/C12 so it's
closer to pin 4. But that really only matters if you expect lot of
RF from cell phones and stuff.
Nope. It's inside a metal box with all the circuit breakers.
That makes
Peter TB Brett wrote:
On Friday 31 October 2008 20:22:59 Joerg wrote:
Might want to rotate C11 and squeeze it in between R18/C12 so it's
closer to pin 4. But that really only matters if you expect lot of
RF from cell phones and stuff.
Nope. It's inside a metal box with all the circuit
Traces from the pin to be decoupled (bypassed) to teh cap should be as
short as possible and as fat as possible. Nothing wrong with making a
small plane out of that because it provides a small additional courtesy
capacitance, for free, to the ground plane below.
Comparison:
On Friday 31 October 2008 03:43:20 pm Joerg wrote:
Much better. If you want to be extra good provide another 0.1uF parallel
to the AVDD caps, close to pin 3. C13 in your channel.sch file. However,
10uF cermamics in SMT are already quite good these days, and cheap. If
you can get C13 closer to
DJ Delorie wrote:
Traces from the pin to be decoupled (bypassed) to teh cap should be as
short as possible and as fat as possible. Nothing wrong with making a
small plane out of that because it provides a small additional courtesy
capacitance, for free, to the ground plane below.
If having to switch between nozzles is a significant issue then there is
room for a new pick and place equipment company that builds a
multi-nozzle tool. In reality, I doubt that it has much of an effect on
cost.
I wonder how the throughput of the pick and place tool compares to the
throughput of
PCB's png exporter has a ben-mode option (yes, we need to rename it)
that does photorealistic output
Is there a reason photorealistic output can't work for the ben-mode
name?
Yes, name things is hard. I've gotten to the point in the Day Job
to coding the name of the project as a function
Is there a reason photorealistic output can't work for the
ben-mode name?
Well, yeah, --photo-mode would work just fine. I just haven't
checked in the change yet.
Yes, name things is hard.
That's why I name everything djfoo :-)
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When Squeezing parts between things, consider what happens at the
assembly stage.
And keep in mind I'm populating these *by hand*.
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On Friday 31 October 2008 08:40:44 pm Steve Meier wrote:
If having to switch between nozzles is a significant issue then there is
room for a new pick and place equipment company that builds a
multi-nozzle tool.
They do exist of course, but there maybe other reasons why
they can't be used in a
Bob Paddock wrote:
On Friday 31 October 2008 03:43:20 pm Joerg wrote:
Much better. If you want to be extra good provide another 0.1uF parallel
to the AVDD caps, close to pin 3. C13 in your channel.sch file. However,
10uF cermamics in SMT are already quite good these days, and cheap. If
you
This could create a problem with the PickPlace machine where your
board
might need two passes on the machine, increasing your assembly
charges.
But only on a vintage machine somewhere in a shed that's heated by a
rickety coal stove ...
Local CM here, where I worked at one
Bob Paddock wrote:
This could create a problem with the PickPlace machine where your
board
might need two passes on the machine, increasing your assembly
charges.
But only on a vintage machine somewhere in a shed that's heated by a
rickety coal stove ...
Local CM
At the end of the day the only thing that counts is whether it's
good enough and it looks like DJ's board should perform pretty well
now.
And yet I keep improving it anyway.
http://www.delorie.com/electronics/powermeter/bypass-2.png
The red ground planes on the left side perhaps aren't
Inspection is moving to aoi automated optical inspection and flying
probe test. Speaking of which the Flying probe test needs locations of
pads and vias and are used to the pad's ascii style file. I have
actually made a lot of progress importing a pads ascii file into pcb and
once I can read the
It isn't your clock that is pulling all that power is it?
Steve M.
On Fri, 2008-10-31 at 22:45 -0400, DJ Delorie wrote:
At the end of the day the only thing that counts is whether it's
good enough and it looks like DJ's board should perform pretty well
now.
And yet I keep improving it
DJ Delorie wrote:
At the end of the day the only thing that counts is whether it's
good enough and it looks like DJ's board should perform pretty well
now.
And yet I keep improving it anyway.
If there's one thing I've learned about working on layouts it's that
you're never really done -
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