On Wednesday 18 February 2009 01:37:13 DJ Delorie wrote:
Pleas read README.cvs
I still think that removing AM_MAINTAINER_MODE from gaf's autoconf was a very
good decision.
Peter
--
Peter Brett
Electronic Systems Engineer
Integral Informatics Ltd
Hello, thanks for looking into it! I'll try the newest git head later
today. Please note that I have constructed some tast cases too and
attached them to the bug tickets.
On Tue, 17 Feb 2009 20:02:42 +
Peter Clifton pc...@cam.ac.uk wrote:
On Mon, 2009-02-16 at 14:58 +0100, Denis Grelich
On Wed, 2009-02-18 at 09:32 +0100, Denis Grelich wrote:
Hello, thanks for looking into it! I'll try the newest git head later
today. Please note that I have constructed some tast cases too and
attached them to the bug tickets.
Ok, thanks.. I've taken a look.
Some are fixed, some remain.
I'm
On Wed, 2009-02-18 at 09:32 +0100, Denis Grelich wrote:
Hello, thanks for looking into it! I'll try the newest git head later
today. Please note that I have constructed some tast cases too and
attached them to the bug tickets.
Btw.. how did the fullpoly flag get set on some polygons in your
I have set the fullpoly flag manually, which wasn't a big deal since I
had to do a lot of manual work in the file (especially when it comes to
arcs -- I was even thinking about writing a patch to be able to work
with arcs sensibly with the GUI, maybe I'll still look into it even
though the board
On Wed, 18 Feb 2009 12:50:11 +
Peter Clifton pc...@cam.ac.uk wrote:
I'm noticing really crappy grid-snap behaviour in the PCB+GL branch at
the moment, especially on your test-case design. Did you test if any
of that grief happen in the non PCB+GL code? The PCB+GL branch also
contains some
On Wed, 2009-02-18 at 15:18 +0100, Denis Grelich wrote:
I have set the fullpoly flag manually, which wasn't a big deal since I
had to do a lot of manual work in the file (especially when it comes to
arcs -- I was even thinking about writing a patch to be able to work
with arcs sensibly with
Changing the clearance on this line breaks the polygon where the
thermal'd via cuts the contour. Uses fullpoly on the polygon to show
the broken fragment(s) which otherwise don't get rendered.
Best wishes,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of
On Wed, 2009-02-18 at 15:05 +, Peter Clifton wrote:
Changing the clearance on this line breaks the polygon where the
thermal'd via cuts the contour. Uses fullpoly on the polygon to show
the broken fragment(s) which otherwise don't get rendered.
Best wishes,
--
Peter Clifton
On Wed, 18 Feb 2009 00:21:08 +
Peter Clifton pc...@cam.ac.uk wrote:
On Tue, 2009-02-17 at 11:29 +0100, Denis Grelich wrote:
On Mon, 16 Feb 2009 12:34:15 -0800
Ben Jackson b...@ben.com wrote:
On Mon, Feb 16, 2009 at 02:56:44PM +0100, Denis
Grelich wrote:
First there's a
On Wed, 2009-02-18 at 21:11 +0100, Denis Grelich wrote:
On Wed, 18 Feb 2009 00:21:08 +
The artifacts seem to be gone, the crashes too. I still get the
disappearing polygon, though.
Yes, that is slightly odd. See the last test-case I posted for a simpler
example of the breakage.
I've not
I have been using the Digilent USB-JTAG cable to program Xilinx devices
and now am working with some Lattice CPLDs in a new project. Does
anyone know of some JTAG programming software that will recognize the
Digilent USB-JTAG cable and allow me to program Lattice parts?
Eric Winsor
On Wed, Feb 18, 2009 at 5:59 PM, Eric Winsor e...@winsor.us wrote:
I have been using the Digilent USB-JTAG cable to program Xilinx devices
and now am working with some Lattice CPLDs in a new project. Does
anyone know of some JTAG programming software that will recognize the
Digilent USB-JTAG
Eric Winsor wrote:
I have been using the Digilent USB-JTAG cable to program Xilinx devices
and now am working with some Lattice CPLDs in a new project. Does
anyone know of some JTAG programming software that will recognize the
Digilent USB-JTAG cable and allow me to program Lattice parts?
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