Am 04.08.2011 21:33, schrieb DJ Delorie:
just log out,
Log out? Log OUT? What's that? ;-)
How do you upgrade kernels?
Philipp
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Am 18.03.2011 03:32, schrieb Dave McGuire:
Tonight I went looking for the latest gnucap development snapshot. The
latest I've been able to find in 2-3mins of googling was from December
of 2009. That can't be right. Al? Pointer?
http://redmine.gnucapplus.org/
Am 08.02.2011 12:17, schrieb John Doty:
On Feb 8, 2011, at 3:48 AM, Stephan Boettcher wrote:
John Doty j...@noqsi.com writes:
I doubt PCB will ever be a suitable tool for chip design.
Why?
Because it's far too ad hoc in its design. It's a collection of
special features, lacking any
Am 08.02.2011 10:14, schrieb Link:
Seeing as 32-bit operating systems (even on 64-bit machines!) are still
widely used, and anything smaller than a nanometre is overkill for the
time being, I'd say playing nice with 32-bit is, at the moment, more
important than making sure people can design
Am 31.12.2010 16:31, schrieb Stephan Boettcher:
Maybe your time is better invested by using a small FPGA for whatever
you want to build, and learn Verilog to express the logic.
Depends how much fun can have from learning such stuff. A deadline does
not seem to be your problem.
(It
I have created a footprint for an edge connector. I created the fingers
the way I would create pads.
However looking at the paste gerber created, this means that solder
paste is put on the fingers, which I don't want.
How can I change this?
Philipp
Am 19.11.2010 23:07, schrieb Colin D Bennett:
It has to be mentioned that Blender is free and open source but Google
Sketchup is not.
Let's not forget other free software, like wings3d, which may be less
powerful compared to blender, but is much more newbie-friendly, and
quite good for
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Am 13.09.2010 09:02, schrieb Oliver King-Smith:
So I want to auto route a design for my ASIC, and magic is being a
little flakey (It seems it connects some nets together that don't
belong and fail to connect nets that do belong). I was
Am 04.09.2010 05:29, schrieb Rick Collins:
XML? What's wrong with XML? Heavy? How heavy are a few electrons anyway?
There is already a preliminary XML based CAD data spec proposed by IPC,
you know, the guys who write specs for the PCB assembly industry...
I don't know if it is the best
Am 04.09.2010 06:19, schrieb Ronald Mathias:
I transform the Verilog code containing behavioral statements into
verilog code that contains only gate level instantiations. This is
passed as input to ABC Logic synthesis tool. Finally the
output generated by ABC is passed to
For a testbench I'd like to read a binary file. However fread() is not
supported in Icarus Verilog. Are there any alternatives?
Philipp
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Is it possible to use Icarus to simplify Verilog code?
I would like to use Berkeley VL2MV/VIS and SIS or ABC, however these
tools understand only a very limited subset to verilog. Can Icarus be
used to synthesize Verilog into a simplified Verilog? SIS and ABC seem
to be a good tools for
I now found a working alternative:
module and2 (A, B, O);
input A ;
input B ;
output O ;
and #(3.62329, 4.98817) (O, A, B);
endmodule
Philipp
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I want to model gate delays, but everything happens without delay.
Icarus gives no errors messages or warnings. I used gates such as the
following:
module and2 (A, B, O);
input A ;
input B ;
output O ;
and (O, A, B);
specify
// delay parameters
specparam
rise =
I would like to use Icarus Verilog for timing simulation. Is this possible?
I would have delay times for gates from another source (probably spice
simulation). I'd like to generate a gate netlist using Icarus and then
simulate it using the delay times. I sthis possible? If no, what would
be the
Michael Sokolov schrieb:
Peter TB Brett pe...@peter-b.co.uk wrote:
* SnPb finish - this one is an absolute requirement for ideological /
philosophical reasons, RoHS crap is *not* acceptable.
In the nicest possible way, WTF?
[...]
The lead-free crap suffers from the severe problem of
Dave McGuire schrieb:
On Jun 9, 2009, at 10:08 PM, Kai-Martin Knaak wrote:
Can someone recommend the easiest
solder to work with (% lead,
No lead.
*PUKE*
I've stocked up on real solder. The unleaded crap sucks.
I've found SnAgCu0.7 as easy for hand soldering as the Sn60Pb I
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KURT PETERS schrieb:
Anyone have any comments on Fritzing?
[1]http://archive.fritzing.org/
Kurt
References
1. http://archive.fritzing.org/
Looking at their website I wonder why they decided to partially reinvent
the wheel and
http://geda.seul.org/wiki/geda:master_attributes_list sys that each pin
needs both a pinnumber and a pinseq. Why? Just so everyone who creates
a symbol using gschem has to click and type twice as much? Is there some
tool that just duplicates the values of pinnumber into pinseq?
Philipp
Well, I just used gschem to make symbols for the 64-pin XC9572 (by
modifying the symbols for the 44-pin XC9532 from gedasymbols.org). It
wasn't that much work. However now I'll have to set all those pinseq values.
Philipp
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Kai-Martin Knaak schrieb:
On Sun, 07 Sep 2008 20:06:21 +0200, Stefan Salewski wrote:
http://www.ssalewski.de/DAD.html.en
Wow, this is ambitious! :-)
An open sourced DSO would be a feat.
Wasn't Bitscope something similar?
Philipp
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der Mouse schrieb:
Anyway, memory is cheap.
Only for mainstream mass-market hardware.
Of course, that may be all gEDA cares about
If we lose users in order to save 1 K, or even 1 Meg of RAM, that
doesn't make sense.
Depends. To what extent is more users an overriding good?
In
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Dave N6NZ schrieb:
An STL file?
If it's just an STL file I suggest wings3d. While not as powerful as
blender it's much easier to learn.
Philipp
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Robert Butts schrieb:
I can't get my printer working yet in Linux and was wondering, in the
interum, is there a way to print gerbers in windows? I'd like to make a
quick two-sided pcb.
Print to a file in Linux. This will give you a .ps or .pdf. You can
convert the .ps to a .pdf. Print the
Tamas Szabo schrieb:
Hello All,
I would like to place a connector to the PCB but I'm unable to put it to
the right position, since no part of the connector can be over the board
outline specified in preferences. I realized it earlier but now it
became significant.
Is there a way to
DJ Delorie schrieb:
When I try to use the global puller on the attached board pcb
20080202 exits.
Old news, lots of boards make it crash.
How come this is board-specific? I'd rather expect it to crash depending
on which lines I selected, but in this board it crashes no matter which
lines I
DJ Delorie schrieb:
Well, if you discovered some new and unique way of crashing it,
perhaps. Otherwise, it's likely you're doing a pull all instead of
pull selected.
pull all always crashes. pull selected crashes whenever I have at
least two line segments selected.
Philipp
Greg Cunningham schrieb:
routed for me (1.8GHz)in 10-15 mins (not sure,... I was fiddling with
another app). I can see about 4 un-routed rats left.
What's your pcb version? Mine is 20080202.
Philipp
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I've just created a pcb footprint, but gsch2pcb can't find it.
I get the error message
1 elements could not be found.
And -v -v shows:
Searching: packages/custom symbols for CVEXTCONN-1
: SIM-1.sym No
: SIM-1.sym~ No
:
DJ Delorie schrieb:
1. file suffixes aren't magic. If it's looking for CVEXTCONN-1 there
needs to be a file called CVEXTCONN-1 available.
2. *.sym are gschem symbols. PCB uses *.fp footprints.
Sorry, I confused the name of the pcb footprint and the geda symbol.
It's working now.
While I've found the autorouter to take some time in the past I now have
a problem where it doesn't seem to complete at all, resulting in a
program hang. The board isn't very complex, the autorouter doesn't
complete in 7 hours on a Core 2 Duo running at 1.2 Ghz.
Philipp
bar.pcb
Description:
Sorry to bump this topic, I hope it will be forgiven if I don't do it a
second time.
Has anyone noticed this problem before?
Philipp
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DJ Delorie schrieb:
As for 10-layer boards and high speed signals, I think anyone with
enough experience to do that is already going to have a set of tools
they'd be comfortable with, and it's hard to convince people to change
- there's very
I have a problem with a layout I just created:
While most of the descriptors can be moved and rotated, this doesn't
work with three of them. Clicking on them with the rotate tool does
nothing. They don't move when I try to drag them with the selection
tool. These tree are capacitor (SIP2 package
Kai-Martin Knaak schrieb:
The components are probably locked.
Thanks. Now it works. Is there some rule about when descriptors are
locked by default?
Philipp
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File attached.
What can I do to open this file in pcb?
Philipp
# release: pcb-bin 20050609
# date:Sat Apr 1 17:07:33 2006
# user:philipp (Philipp Klaus Krause,,,)
# host:localhost.localdomain
PCB[L1.2 158300 165500]
Grid[1000. 0 0 1]
Cursor[97400 85800 2.00]
Thermal
I'm a bit confused about the different types gold surface finish. AFAIR
immersion gold is thicker than the other two, but I don't know more. How
do they compare in price and reliability?
Philipp
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I've just created a simple layout using gschem, gsch2pcb and pcb. I've
rotated some elements using cut to buffer, rotate, paste. This rotated
the elementes including their reference designators. How can I rotate
the reference designators back? Now I have a C4 facing the other way
compared to C2.
Philipp Klaus Krause schrieb:
I have a problem in a recently created schematic:
gschem2pcb creates a netlist where +5V and GND are connected together.
I do not see such a connection in the schematic (5V stuff is in the
lower left corner only, VCC is +3.3V)
gschem2pcb worked initially
I have a problem in a recently created schematic:
gschem2pcb creates a netlist where +5V and GND are connected together.
I do not see such a connection in the schematic (5V stuff is in the
lower left corner only, VCC is +3.3V)
gschem2pcb worked initially, then I realized that pins on the voltage
I just updated my pcb version to 20070208. When I load a design there
are descriptions like U1, R1, CONN1, etc near the components now.
I don't want these. How can I get rid of them?
Philipp
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DJ Delorie schrieb:
I just updated my pcb version to 20070208. When I load a design
there are descriptions like U1, R1, CONN1, etc near the
components now. I don't want these. How can I get rid of them?
Um, pcb should have been showing those all along. I don't think you
can hide *just*
Andy Peters schrieb:
I suspect that most people would prefer to see a refdes instead of a
value on the silkscreen.
I probably could live with refdes near resistors, capacitors and chips,
but I really don't want the CONN1 - it's just the card edge that is
inserted into a slot, no compoent
DJ Delorie schrieb:
Menu: View-Value
Of course, that assumes you've set up the values to begin with. I
think it copies the value attribute from gschem, but I rarely look
at the values in pcb anyway.
Hmm, now it says 10K near the resistor, .22 followed by two black
boxes - I assume pcb
Predrag Bradaric wrote:
Hi.
I'm new to this group and 'world' of HDL.
I worked with Altera's QUARTUS - designing some simple applications in
AHDL and VHDL (really, on a basic level).
That's when I saw the power of FSM in designing 'simple' logic
circuits, and power of VHDL in designing
I'm currently drawing a schematic using gschem. There's a GAL in it and
some other chips. Since the GAL's outputs /inputs are all equivalent I
don't care which output is used for some task. For example I want to
feed a GAL output into the output enable of an EPROM. So I want one of
the GAL's
I'm creating my first schematic using gschem (previously I schematics
were in my head or on paper only and I only used pcb to create the pcb
layout).
I've drawn lots of nets when I noticed the button for busses. How do I
use these (the documentation only states Buses are very new and there
are
Steve Meier schrieb:
Philipp,
Standard gshem and gnetlist (gsch2pcb) treat buses as a graphical object
that doesn't influence the final netlist in anyway.
If your design is flat hook up a net segment from a components pin to
the bus. Select the net segment and add a net attribute net=D0
Is Icarus PAL still alive? if not is there maintained free software to
program the 22V10?
Philipp
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John Coppens schrieb:
'Static' is normally reserved to specify the data should never be
destroyed by the compiler if the compiler thinks it's not necessary any
more (eg. to make data 'static', i.e. available between function calls to
the same
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