.
Regards,
Ronald
On 9/5/10, Ronald Mathias [1]ronnie.math...@gmail.com wrote:
Hi,
Thanks a lot.
Regards
Ronald Mathias
On 9/4/10, Philipp Klaus Krause [2]...@spth.de wrote:
Am 04.09.2010 06:19, schrieb Ronald Mathias:
I transform
Hi,
Thanks a lot.
Regards
Ronald Mathias
On 9/4/10, Philipp Klaus Krause [1]...@spth.de wrote:
Am 04.09.2010 06:19, schrieb Ronald Mathias:
I transform the Verilog code containing behavioral statements
into
verilog code that contains
Hi,
I have written a verilog code that makes use of a user defined task to
do some computation. The task takes two parameters as input and one
parameter as output.
When I try to synthesize it, I get the following error:
internal error: NetProc::nex_output not implemented
-Original Message-
From: [8]geda-user-boun...@moria.seul.org [mailto:[9]geda-user-
[10]boun...@moria.seul.org] On Behalf Of Ronald Mathias
Sent: Monday, July 12, 2010 11:15 PM
To: [11]geda-u...@moria.seul.org
Subject: gEDA-user: Chortle
Hi,
Could any one tell me from where I can download the source code for
Chortle: A Technology Mapping Program for Lookup Table-Based Field
Programmable Gate Arrays program.
I have tried searching for it on google. I only get the pdf file that
describes the program but I am
Hi,
I just wanted to know if anyone knows any good books that describe RTL
synthesis algorithms. I know about books on Logic synthesis. Logic
synthesis books only describe about optimizing gate level descriptions.
I am not interested in them.
I am particularly interested in
Hi,
I have downloaded the windows version of icarus verilog version 0.8.1.7
from [1]http://bleyer.org/icarus/. When I install the executable, I get
the executable vlpp.exe ivl.exe. in the lib\ivl directory. I know that
vlpp.exe is the preprocessor. But I do not know what is
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