Stephan Boettcher wrote:
> I do not like the part about removing footprints on copy.
Maybe you like it better, if I call it "move existing footprints
to the location indicated by the buffer" ;-)
---<)kaimartin(>---
--
Kai-Martin Knaak
Öffentlicher PGP-Schlüssel:
http://pgp.mit.edu:11371/pks/lo
kai-martin knaak writes:
> Larry Doolittle wrote:
>
>>> All the cutting, sed-ing and pasting of the subcircuits to multiple
>>> instances, with replication of later changes on all copies is pretty
>>> unflexible.
>>
>> Agree 100%.
>
> +1
>
> Cloning, referencing, or whatever we may call it, woul
> Thanks for that script. I like the way you load the netlist and save.
> So, whenever you think of a little change to the repeated cell, just
> remake the board with the script, then run DRCs on it, and output.
That's what I did. I had one .pcb that was one channel, and one that
was everything
DJ Delorie wrote:
Does what's pasted from the buffer stay selected?
Yes. I used it with a pcb script on the powermeter board. Each
renumber adds 10 to whatever's in the buffer...
Thanks for that script. I like the way you load the netlist and save.
So, whenever you think of a little change
> Does what's pasted from the buffer stay selected?
Yes. I used it with a pcb script on the powermeter board. Each
renumber adds 10 to whatever's in the buffer...
LoadFrom(Layout,powermeter-blank.pcb)
LoadFrom(LayoutToBuffer,channel1.pcb)
# left upper, first one already there
# First is at 20
DJ Delorie wrote:
That's a great idea for low-effort/high-value.
At least for those of us who array things on mere boards
instead of chips...
http://www.delorie.com/pcb/renumberblock.c
Hmm... looks like that would work good for things I can select easily.
Does what's pasted from the buffer s
> That's a great idea for low-effort/high-value.
> At least for those of us who array things on mere boards
> instead of chips...
http://www.delorie.com/pcb/renumberblock.c
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kai-martin knaak wrote:
In the meantime, a more powerful copy procedure could reduce
the effort:
Imagine, the copy-buffer action would accept a string parameter
that it adds to the refdes property of every footprint before
actually pasting to the layout. If this string matches the
string gnetlis
Larry Doolittle wrote:
>> All the cutting, sed-ing and pasting of the subcircuits to multiple
>> instances, with replication of later changes on all copies is pretty
>> unflexible.
>
> Agree 100%.
+1
Cloning, referencing, or whatever we may call it, would need
a fair amount of programming. Give
Ouabache Designworks wrote:
> Asic synthesis has a step called "uniquification" where you create a module
> and
> instantiate it multiple times. Uniquify will create a new module for each
> instance
> that can be modified independently from the others. You can also modify the
> master to chang
Using blocks in mechanical CAD has some issues with this. In
principle
there are 2 ways to use a block:
a) copy and paste
b) reference
Naturally the "edit one modify all" can only work with referencing.
Sometimes in a single construction this is not desired,
On Mon, Aug 16, 2010 at 07:32:23PM +0200, Stephan Boettcher wrote:
> I usually have hierarchical schematics with multiple instances of the
> same subcircuits referenced from the main page. The deepest until now
> were three layers of hierarchy.
I make do with two, but that's how I work also.
> A
Stephan Boettcher wrote:
Stefan Salewski writes:
On Mon, 2010-08-16 at 10:09 +0200, Stephan Boettcher wrote:
John Griessen writes:
If there is work put into partitioning a layout, can't we please have
hierarchical layout instead?
I have still problems to understand the go
Stefan Salewski writes:
> On Mon, 2010-08-16 at 10:09 +0200, Stephan Boettcher wrote:
>> John Griessen writes:
>>
>> If there is work put into partitioning a layout, can't we please have
>> hierarchical layout instead?
>>
> I have still problems to understand the goals and benefits of
> partit
Stephan Boettcher wrote:
John Griessen writes:
net attribs plus layout zones get us far
on the way to autorouting success.
If there is work put into partitioning a layout, can't we please have
hierarchical layout instead?
They are independent enough that it's not a choice of either or.
Bot
On Mon, 2010-08-16 at 10:09 +0200, Stephan Boettcher wrote:
> John Griessen writes:
>
> > It's not pie in the sky. Some of these ideas to use sets and lists
> > and groups are the easiest kind to implement... Zones in layout are
> > an easy part of what it already does, when we have more layers
John Griessen writes:
> It's not pie in the sky. Some of these ideas to use sets and lists
> and groups are the easiest kind to implement... Zones in layout are
> an easy part of what it already does, when we have more layers for
> intermediate calculations. net attribs plus layout zones get u
Rick Collins wrote:
This pie-in-the-sky stuff is fine, but I can see much more utility
coming from more mundane developments.
It's not pie in the sky. Some of these ideas to use sets and lists
and groups are the easiest kind to implement... Zones in layout are
an easy part of what it already
Stefan Salewski wrote:
OK, one more, but very special case,
where subnets may be useful: We can have nets of 3 nodes, where we want
a linear shape, not a T or star shape. For this case we may define one
subnet from pin 1 to 2, and one more from 2 to 3. We make these two
subnets not compatible, so
Rick Collins wrote:
First, I want to say that power supply bypassing is probably not a good
example to use since there are a number of ways to layout such things
and many people will disagree about the "optimal" way of doing it.
I think it's an OK example. There's no need to assume any way of
On Sun, 2010-08-15 at 16:43 -0400, Rick Collins wrote:
> At 04:27 PM 8/15/2010, you wrote:
> >On Sun, 2010-08-15 at 15:43 -0400, Rick Collins wrote:
> >
> >For details see the related posting in this list...
>
> Maybe you are missing my point. What value does the subnet have if
> the layout TOO
At 04:27 PM 8/15/2010, you wrote:
On Sun, 2010-08-15 at 15:43 -0400, Rick Collins wrote:
>
> First, I want to say that power supply bypassing is probably not a
> good example to use since there are a number of ways to layout such
> things and many people will disagree about the "optimal" way of d
On Sun, 2010-08-15 at 15:43 -0400, Rick Collins wrote:
>
> First, I want to say that power supply bypassing is probably not a
> good example to use since there are a number of ways to layout such
> things and many people will disagree about the "optimal" way of doing
> it. Perhaps a more gener
At 03:03 PM 8/15/2010, you wrote:
On Sun, 2010-08-15 at 14:10 -0400, Rick Collins wrote:
> I see we are talking about two different things. I was responding to
> Andrew's post about splitting nets into portions with different
> properties. In my way of thinking if they have different properties
On Sun, 2010-08-15 at 21:03 +0200, Stefan Salewski wrote:
> attributes/class). For my picture P1 is a common point of these subnets.
> One restriction is: This subnet with property bypass shall be short, low
> impedance.
Sorry, I forgot:
Points which connects subnets will be always pads or pins o
On Sun, 2010-08-15 at 14:10 -0400, Rick Collins wrote:
> I see we are talking about two different things. I was responding to
> Andrew's post about splitting nets into portions with different
> properties. In my way of thinking if they have different properties,
> they should be separate nets.
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