Re: gEDA-user: [Icarus Verilog] Unable to synthesize synchronous process

[EMAIL PROTECTED] wrote: Good day! I'm just a NB in Verilog design, sorry if my question is too stupid :) I've started with free Xilinx ISE, but now i'm trying to do my best to take part in icarus verilog community. I became familiar with IV modelling system, but synth restrain my

gEDA-user: [Icarus Verilog] Unable to synthesize synchronous process

Good day! I'm just a NB in Verilog design, sorry if my question is too stupid :) I've started with free Xilinx ISE, but now i'm trying to do my best to take part in icarus verilog community. I became familiar with IV modelling system, but synth restrain my activity - i get strange error with the

Re: gEDA-user: [Icarus Verilog] Unable to synthesize synchronous process

On Tue, Jun 03, 2008 at 02:09:34AM +0400, [EMAIL PROTECTED] wrote: I've started with free Xilinx ISE, but now i'm trying to do my best to take part in icarus verilog community. Welcome! iverilog -tfpga test.v test.v:7: sorry: Forgot to implement NetCondit::synth_sync test.v:6: error: Unable