Adam Megacz wrote:
I believe we now have the
first-ever instance of a design being taken through a 100% open-source
flow, all the way from verilog to blinking lights on a programmed device.
Thanks for reporting this here. I'm interested in using your devel board
to get introduced to using
On Jul 28, 2007, at 6:05 PM, John Griessen wrote:
I believe we now have the
first-ever instance of a design being taken through a 100% open-
source
flow, all the way from verilog to blinking lights on a programmed
device.
Thanks for reporting this here. I'm interested in using your
Please bear in mind that this is only an 8-bit ripple-carry adder, and
the tools are still quite crude, but I believe we now have the
first-ever instance of a design being taken through a 100% open-source
flow, all the way from verilog to blinking lights on a programmed device.
Details are here:
Stephen Williams [EMAIL PROTECTED] writes:
The v0.8 releases of Icarus Verilog have decent synthesis. The
synthesis is not at all Xilinx specific, but the code generators
are. But they needn't be. The FPGA target generates EDIF, so if
your intermediate form takes EDIF, the way to move forward
Stephen Williams [EMAIL PROTECTED] writes:
The v0.8 releases of Icarus Verilog have decent synthesis. The
synthesis is not at all Xilinx specific, but the code generators
are. But they needn't be. The FPGA target generates EDIF, so if
your intermediate form takes EDIF, the way to move forward
Adam Megacz wrote:
Stephen Williams [EMAIL PROTECTED] writes:
The v0.8 releases of Icarus Verilog have decent synthesis. The
synthesis is not at all Xilinx specific, but the code generators
are. But they needn't be. The FPGA target generates EDIF, so if
your intermediate form takes EDIF, the
Stephen Williams [EMAIL PROTECTED] writes:
One difficulty, though: the primitive cells that iverilog emits are
pretty complex. Is there any way to ask it to break down multipliers
and adders into stuff no larger than a LUT4?
The reason it generates at that level is that in some cases it
is
So, now that the abits work is published [1] I plan on turning my
attention to connecting the dots, so to speak.
I've pretty much resigned myself to the fact that I'll have to
implement PAR by hand (VPR has licensing issues, and there are far
more architecture-portable algorithms now anyways
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