Part of the conceptual difficulty here is that network theory can't
tackle these issues very well. To really understand circuits you need
to use physical optics: a circuit board is a collection of coupled
waveguides. Network theory is the long wavelength limit of physical
optics, but the
On Tue, Oct 20, 2009 at 4:38 AM, Gabriel Paubert paub...@iram.es wrote:
I have done some testing of various passives (mostly 0402) and came to
the conclusion. I tested both shunt and series capacitors on a 50 ohm
transmission line with a VNA. What was most interesting to me was that
the large
On Mon, Oct 19, 2009 at 03:18:25PM +0100, Andy Fierman wrote:
So your consultant thinks it's a bad idea to have a Vcc plane because
it takes up space that you could use for additional ground planes and
that you might need to run traces ...
... and then urges you to run power traces where?
On Mon, Oct 19, 2009 at 10:07:00AM -0500, John Griessen wrote:
Andy Fierman wrote:
So your consultant thinks it's a bad idea to have a Vcc plane because
it takes up space
.
.
.
Hopefully you can gently persuade your boss that this is not quite
what the very expensive consultant
On Mon, Oct 19, 2009 at 10:50:49AM -0400, Gene Heskett wrote:
On Monday 19 October 2009, Bob Paddock wrote:
Boss just sent around something he got from a consultant on
doing proper EMI design (which I've been doing for years already,
I thought until consultant came up with this):
Eliminate
On Mon, Oct 19, 2009 at 06:43:42PM -0500, Darrell Harmon wrote:
On Mon, Oct 19, 2009 at 5:27 PM, Dan McMahill d...@mcmahill.net wrote:
my recent experiences are more in line with Larry's. Most C for a given
package and voltage seems to be the best meaning that above resonance it
is no
There are some nice little tools to show the behaviour of multilayer
chip ceramics (and some of Murata's inductors)
Although they don't include their single layer microwave caps in the
database, the Murata Chip Capacitor and Inductor S-Parameter
Impedance Library program from here:
Darrell Harmon wrote:
I like to use 3 terminal feedthrough capacitors when I am concerned
about frequencies 1 GHz getting on the power supply.
yes. Those are your friends! I like to stick those in the mouse hole
on a shield can.
-Dan
___
Boss just sent around something he got from a consultant on
doing proper EMI design (which I've been doing for years already,
I thought until consultant came up with this):
Eliminate separate Vcc planes.
This ancient practice is long overdue for an overhaul. Years ago, the
leaded capacitors were
So your consultant thinks it's a bad idea to have a Vcc plane because
it takes up space that you could use for additional ground planes and
that you might need to run traces ...
... and then urges you to run power traces where?
In the - now empty - Vcc plane layer?
Or in the same layer as your
On Monday 19 October 2009, Bob Paddock wrote:
Boss just sent around something he got from a consultant on
doing proper EMI design (which I've been doing for years already,
I thought until consultant came up with this):
Eliminate separate Vcc planes.
What's he/she smoking, it must be great stuff
Andy Fierman wrote:
So your consultant thinks it's a bad idea to have a Vcc plane because
it takes up space
.
.
.
Hopefully you can gently persuade your boss that this is not quite
what the very expensive consultant meant to say.
So, are there no conditions where leaving out a VCC plane
I can't suggest much that hasn't been already stated.
A good reference book Printed Circuit board design techniques for
EMC compliance (ISBN0-7803-5376-5) it has interesting advice about
different layre stackups and the effects on inductance and decoupling
(now 9 years old but still in print)
for clarification:
... you might imagine times when routing thick
tracks as differential pairs with the ground plane on signal layres [instead
of a Vcc plane].
would make the design less likely to have ground loops or mistakenly
mistakenly
violate moating.
On Mon, Oct 19, 2009 at 08:35:33AM -0400, Bob Paddock wrote:
To me running Vcc traces all over the board is the surest way to raise
inductance etc., and seems wrong to me.
Plus in high current, low voltage designs (like FPGA core power) the tiny
series resistance of even a plane can be a
)
--
Message: 1
Date: Mon, 19 Oct 2009 08:35:33 -0400
From: Bob Paddock graceindustr...@gmail.com
Subject: gEDA-user: Eliminate separate Vcc planes?
To: gEDA user mailing list geda-user@moria.seul.org
Message-ID:
a3aee9a50910190535gc14d760t7e6d55f830cc6
Neil -
On Mon, Oct 19, 2009 at 01:20:23PM -0700, Neil Hendin wrote:
If you look at the RF S-Parameters of the capacitor at frequencies
above the self resonance, they look inductive, not capacitive.
I'm not sure what the precise definition is for the S-Parameters
of a two-terminal device, but
I second this request. All of the quantitative data that I have seen
basically says that for a given dielectric, the inductance is a
function of the package size and shape regardless of the capacitance.
And yet the rule of thumb continues to be mixing capacitor values to
handle a range of
Larry Doolittle wrote:
Good RF decoupling standard practice is to use a smaller cap
(e.g. 20pF in parallel with some larger ones such as 1000pF
_and_ 0.1uF or larger as needed) to get a good broad band
capacitive reactance across frequency).
I have yet to see a 20pF or 1000pF cap with less
On Mon, Oct 19, 2009 at 5:27 PM, Dan McMahill d...@mcmahill.net wrote:
my recent experiences are more in line with Larry's. Most C for a given
package and voltage seems to be the best meaning that above resonance it
is no worse than smaller capacitance value devices and below resonance
it is
On Monday 19 October 2009, Dan McMahill wrote:
Larry Doolittle wrote:
Good RF decoupling standard practice is to use a smaller cap
(e.g. 20pF in parallel with some larger ones such as 1000pF
_and_ 0.1uF or larger as needed) to get a good broad band
capacitive reactance across frequency).
I
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