Jared Casper wrote:
> http://www.gnu.org/software/guile/manual/html_node/Hook-Reference.html
>
> Looks like there is a remove-hook! function, or just reset-hook! and
> start over with what you want.
Thank you for the pointer! I tried reset-hook! and it did the job.
---<)kaimartin(>---
--
Kai-
On Tue, Sep 13, 2011 at 1:30 PM, Kai-Martin Knaak
wrote:
> Some hooks of gschem are hooked in by default in system-gschemrc. Most of
> these are fine. But some don't mix well with my style of schematics (e.g.
> autoplace-object-attributes)
>
> Is there a way to unhook these short of editing system
Some hooks of gschem are hooked in by default in system-gschemrc. Most of
these are fine. But some don't mix well with my style of schematics (e.g.
autoplace-object-attributes)
Is there a way to unhook these short of editing system-gschemrc? I thought
about overloading with some kind of NOP script
> Why are you all looking for an algorithm? Since pcb warns, it
> _already_ found the short. So the algorithm is already in place and
> is working fine.
It hasn't found a short, it has found that two nets are connected
which shouldn't be. Subtle difference, but it's a big deal when
you're trying
On Sat, Sep 03, 2011 at 07:15:05AM +1000, Stephen Ecob wrote:
> > A similar solution in PCB would be neat. if VCC and GND are shorted,
> > pick a random GND pin and a random VCC pin. Find a path between them
> > and show it as a orange dotted line. This could later be extended to
> > find either th
Hi Thomas,
> -Original Message-
> From: geda-user-boun...@moria.seul.org
> [mailto:geda-user-boun...@moria.seul.org] On Behalf Of Thomas Oldbury
> Sent: Friday, September 02, 2011 3:17 PM
> To: gEDA user mailing list
> Subject: Re: gEDA-user: How to find which specifi
> I remember the old Quake maps had to be "sealed", so any loose seam
> would cause problems. Because the map editor doesn't know what you
> meant to be outside/inside, etc, the map editor had a feature to deal
> with this, it would create a line that would start in one area, and
> head to another.
>
> Since we have such a good, algorithmic method for finding these shorts,
> perhaps we can write some code to do it for our puny human minds? ;)
>
> Usually, when I have power and ground shorted, it's because of a via placed
> some where that was accidentally assigned thermals to the wrong layer
> wouldn't it be nice to be able to tell a polygon that it belongs to
> a net and the have the thermals that disagree highlighted?
Yes, it would :-)
I thought of an idea for a plugin... starting with each pin/pad, trace
connections back to the next intersection (rather than blindly finding
the *
On Fri, Sep 2, 2011 at 11:16 PM, Thomas Oldbury wrote:
> When I delete the shorted objects (a microSD card connector, and a 3
> pin header) the short location moves!!
> I can't see a short anywhere on this board. I've searched the PCB file
> for shorted thermals, no luck.
> Is there a pa
I don't know if this will help or not, but here goes...
I've never used net highlighting in PCB before, but I had a similar
problem in an ASIC designed using Cadence's Virtuoso layout editor. I
ultimately tracked it down using the "highlight trace" feature of the
program, which included the nifty
Unfortunately, the highlighting just tells you WHICH nets are shorted,
not where they are shorted.
I tried deleting the objects in question which highlight orange. Now it
just highlights some more objects orange indicating 3.3V and ground are
shorted somewhere.
Is there any way to
wouldn't it be nice to be able to tell a polygon that it belongs to a
net and the have the thermals that disagree highlighted?
On Fri, 2011-09-02 at 15:13 +1000, Stephen Ecob wrote:
> > Usually, when I have power and ground shorted, it's because of a via placed
> > some where that was accidentally
> Usually, when I have power and ground shorted, it's because of a via placed
> some where that was accidentally assigned thermals to the wrong layer.
>
> -Ethan
+1
Often when this happens I find it easiest to fix in a text editor,
it's easier to spot a via connected to too many layers there than
On 08/31/2011 07:09 PM, Kai-Martin Knaak wrote:
Thomas Oldbury wrote:
I am getting these messages:
Warning! Net "3V3plus" is shorted to net "GND"
Warning! Net "GND" is shorted to net "3V3plus"
The 3.3V bus is used all over the board. How can I locate
specifically which part is shorted?
This
Thomas Oldbury wrote:
> I am getting these messages:
>
> Warning! Net "3V3plus" is shorted to net "GND"
> Warning! Net "GND" is shorted to net "3V3plus"
>
> The 3.3V bus is used all over the board. How can I locate
> specifically which part is shorted?
This is what I do:
1) open the net list w
On Thu, Sep 1, 2011 at 8:39 AM, John Griessen wrote:
> On 08/31/2011 04:57 PM, Thomas Oldbury wrote:
>
>> The 3.3V bus is used all over the board. How can I locate specifically
>> which part is shorted?
Keep an eye out for orange highlights - for example a via with an
orange ring around it.
On 08/31/2011 04:57 PM, Thomas Oldbury wrote:
The 3.3V bus is used all over the board. How can I locate specifically
which part is shorted?
Divide and conquer...delete some trace segments or reroute 2 pieces where one
long one is
and see what changes...
It must be something I placed
I am getting these messages:
Warning! Net "3V3plus" is shorted to net "GND"
Warning! Net "GND" is shorted to net "3V3plus"
The 3.3V bus is used all over the board. How can I locate specifically
which part is shorted? It must be something I placed recently, but I do
not have an und
On Thu, 25 Aug 2011, Colin D Bennett wrote:
On Wed, 24 Aug 2011 16:33:05 -0400 (EDT)
Cory Papenfuss wrote:
Thanks for all the suggestions. I've played with it a bit
and come up with an example for a 200mil radial capacitor below:
Element["" "" "C0" "" 97000 208000 8000 -28000 0 100
On Wed, 24 Aug 2011 16:33:05 -0400 (EDT)
Cory Papenfuss wrote:
> Thanks for all the suggestions. I've played with it a bit
> and come up with an example for a 200mil radial capacitor below:
>
> Element["" "" "C0" "" 97000 208000 8000 -28000 0 100 ""]
> (
> Pin[0 0 0 3000 6600 300
Colin D Bennett wrote:
> Well, you could do the heavy lifting with an awk script:
>>
>> If the current line is a pin,
>> set the diameter of the pin to zero and add a hole flag
>> ouput a round pad with the diameter of the pins annular ring
>> else,
>> output the current line unc
Colin D Bennett wrote:
>> Well, you could do the heavy lifting with an awk script:
>>
>> If the current line is a pin,
>> set the diameter of the pin to zero and add a hole flag
>> ouput a round pad with the diameter of the pins annular ring
>> else,
>> output the current line unc
Thanks for all the suggestions. I've played with it a bit and
come up with an example for a 200mil radial capacitor below:
Element["" "" "C0" "" 97000 208000 8000 -28000 0 100 ""]
(
Pin[0 0 0 3000 6600 3000 "" "1" "hole,square"]
Pin[2 0 0 3000 6600 3000 "" "2" "hole"]
On Tue, 23 Aug 2011 22:53:23 +0200
Kai-Martin Knaak wrote:
> Cory Papenfuss wrote:
>
> > I thought about that... making different footprints that don't
> > have copper on the component side of the pins. Since that would
> > require making new footprints for pretty much everything,
>
> Well, y
Cory Papenfuss wrote:
> I thought about that... making different footprints that don't
> have copper on the component side of the pins. Since that would require
> making new footprints for pretty much everything,
Well, you could do the heavy lifting with an awk script:
If the current line i
On Tue, 2011-08-23 at 13:52 -0400, Cory Papenfuss wrote:
> I thought about that... making different footprints that don't
> have copper on the component side of the pins. Since that would require
> making new footprints for pretty much everything, I was hoping for a
> different solution..
I thought about that... making different footprints that don't
have copper on the component side of the pins. Since that would require
making new footprints for pretty much everything, I was hoping for a
different solution... :) It seems like it would be a relatively common
thing for hobbyis
On Tue, 23 Aug 2011 07:15:54 -0400 (EDT)
Cory Papenfuss wrote:
> Hey, all. I've used PCB on an off for 10 years and recently
> have been getting familiar again with the rest of gEDA which has
> become a great set of tools!
>
> Anyway, I've been using a board mill to make 1 and 2-lay
Hey, all. I've used PCB on an off for 10 years and recently have
been getting familiar again with the rest of gEDA which has become a great
set of tools!
Anyway, I've been using a board mill to make 1 and 2-layer
prototypes of typically through-hole components. The trouble is when the
aut
Hello,
Some XSPICE models have vector inputs and vector outputs. In such
cases, how to make gnetlist generate the correct netlist by putting the
node numbers or names within square brackets like this: [1 2 ]
Thanks for your help.
Anand
--
Close Windows ! Open source !!
F
Hello,
Some XSPICE models have vector inputs and vector outputs. In such
cases, how to make gnetlist generate the correct netlist by putting the
node numbers or names within square brackets like this: [1 2 ]
Thanks for your help.
Anand
--
Close Windows ! Open source !!
Dear Kai-Martin,
Thanks for your information. I will contact DJ.
Sincerely,
RSA
On Tue, Jul 12, 2011 at 5:06 AM, Kai-Martin Knaak
<[1]k...@familieknaak.de> wrote:
Ananda Murthy R S wrote:
> I have noticed that XSPICE code models do not have corresponding
symbols. I
Ananda Murthy R S wrote:
> I have noticed that XSPICE code models do not have corresponding symbols. I
> have prepared symbols for these code models. How to submit them to be
> included in the official distribution of gEDA Suite?
The default lib is currently not maintained. Additions have not bee
Hello,
I have noticed that XSPICE code models do not have corresponding
symbols. I have prepared symbols for these code models. How to submit
them to be included in the official distribution of gEDA Suite?
Anand
--
Close Windows ! Open source !!
Free software from proprietar
2011/5/2 Rob Butts :
> So, how can I find those symbols? That means that if I don't use the
> VDD and VSS nets I have to copy all symbols into my own symbol
> directory? Wow, that is an inconvenience to say the least; especially
> where I will never use VDD or VSS. There's no other way t
John Doty wrote:
>> locate -i lm317 | grep .sym
>>
>> should give the same result, with less consume of resources.
>> Indeed "| grep .sym" should be obsolete here.
>
> Close, but grep treats the "." as a wildcard,
I'd locate the symbols like this:
locate *lm317*.sym
If there is no wildcard c
On Mon, 2011-05-02 at 14:08 -0600, John Doty wrote:
> On May 2, 2011, at 1:58 PM, Stefan Salewski wrote:
>
> > On Mon, 2011-05-02 at 13:49 -0600, John Doty wrote:
> >
> >>
> >> locate .sym | grep -i lm317
> >>
> >
> > locate -i lm317 | grep .sym
> >
> > should give the same result, with less
On May 2, 2011, at 2:09 PM, Rob Butts wrote:
> What does | grep .sym do?
In a Unix-derived command shell "a | b" runs sends the output of program "a" to
program "b" as input. "grep" is a program that filters its input, yielding
lines that match a pattern, in this case ".sym". Type "man grep"
What does | grep .sym do?
On Mon, May 2, 2011 at 3:58 PM, Stefan Salewski <[1]m...@ssalewski.de>
wrote:
On Mon, 2011-05-02 at 13:49 -0600, John Doty wrote:
>
> locate .sym | grep -i lm317
>
locate -i lm317 | grep .sym
should give the same result, with less consume
On May 2, 2011, at 1:58 PM, Stefan Salewski wrote:
> On Mon, 2011-05-02 at 13:49 -0600, John Doty wrote:
>
>>
>> locate .sym | grep -i lm317
>>
>
> locate -i lm317 | grep .sym
>
> should give the same result, with less consume of resources.
> Indeed "| grep .sym" should be obsolete here.
Cl
On Mon, 2011-05-02 at 13:49 -0600, John Doty wrote:
>
> locate .sym | grep -i lm317
>
locate -i lm317 | grep .sym
should give the same result, with less consume of resources.
Indeed "| grep .sym" should be obsolete here.
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On May 2, 2011, at 1:36 PM, Rob Butts wrote:
> So, how can I find those symbols? That means that if I don't use the
> VDD and VSS nets I have to copy all symbols into my own symbol
> directory? Wow, that is an inconvenience to say the least; especially
> where I will never use VDD or VSS.
So, how can I find those symbols? That means that if I don't use the
VDD and VSS nets I have to copy all symbols into my own symbol
directory? Wow, that is an inconvenience to say the least; especially
where I will never use VDD or VSS. There's no other way to save them
in their o
The nets are in there but I suspect it's not letting save and exit the
schematic because it won't let me save the symbols; which is probably
why those nets are still in the netlist.
On Mon, May 2, 2011 at 3:19 PM, DJ Delorie <[1]d...@delorie.com> wrote:
Save the pcb file and look
On May 2, 2011, at 1:18 PM, Rob Butts wrote:
> I just went into each symbol in my schematic and changed the VDD:xx to
> Vcc:xx and VSS:xx to GND:xx. I then save the schematic and ran
> gsch2pcb and when I bring up the netlist it still has the VSS and VDD
> nets. It shouldn't because no
Save the pcb file and look at it; near the end will be the netlist and
you can search it for the mystery nets.
Or look at the *.net file.
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I just went into each symbol in my schematic and changed the VDD:xx to
Vcc:xx and VSS:xx to GND:xx. I then save the schematic and ran
gsch2pcb and when I bring up the netlist it still has the VSS and VDD
nets. It shouldn't because no symbol has those nets. I then went to
quit the
The symbols for the logic came from the 4000 series logic library in
gshem. I'm glad I realized this because the design wouldn't have
worked.
On Mon, May 2, 2011 at 2:43 PM, DJ Delorie <[1]d...@delorie.com> wrote:
If you have different symbols with different names for the same n
If you have different symbols with different names for the same net, you'll
have to rename
them to all have the same net, yes.
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Actually, to get the GND net to tie in with the VSS net do I have to go
down into each symbol in gschem and replace net=VSS:8 with net=GND:8?
Same with Vcc and VDD?
On Mon, May 2, 2011 at 2:21 PM, DJ Delorie <[1]d...@delorie.com> wrote:
> 1. How do I set up the groups and layers i
> 1. How do I set up the groups and layers in preferences for 3
> signal planes and the one groub?
In PCB there's no real difference between a signal plane and a
power/gnd plane. Just set up any 4-layer board.
> 2. Once I create the rectangle of the ground plane, how do I get
> PCB to attach
I'd like to make a 4-layer board with a ground plane that all the GND
net and VSS net connect to. I've read through DJ's PCB tutorial but
I'm not clear about a few things.
1. How do I set up the groups and layers in preferences for 3 signal
planes and the one groub?
2. Once I c
Thank you!
That did it.
On Fri, Apr 29, 2011 at 5:24 PM, DJ Delorie <[1]d...@delorie.com> wrote:
You have to remove the 'T' line just before the text too
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[3]http://www.seu
You have to remove the 'T' line just before the text too
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I removed that line from the text and now I'm see "N 55500 45200 53300
45200 4" on the schematic where the U9 was. Should I just select that
text in the schematic and delete it? I don't feel comfortable doing
that. Are all those lines between what appears to be two capacitor
state
Mark Rages writes:
> On Fri, Apr 29, 2011 at 3:03 PM, Rob Butts wrote:
>> Having never looked at a schematic this way I wouldn't know what to
>> look for but from this excerpt can you tell if this is just a stray
>> refdes that doesn't belong? It is the only U9 found.
>
>
> Right, looks l
Will do!
On Fri, Apr 29, 2011 at 4:09 PM, Mark Rages <[1]markra...@gmail.com>
wrote:
On Fri, Apr 29, 2011 at 3:03 PM, Rob Butts <[2]r.but...@gmail.com>
wrote:
> Having never looked at a schematic this way I wouldn't know what to
> look for but from this excerpt can you te
On Fri, Apr 29, 2011 at 3:03 PM, Rob Butts wrote:
> Having never looked at a schematic this way I wouldn't know what to
> look for but from this excerpt can you tell if this is just a stray
> refdes that doesn't belong? It is the only U9 found.
Right, looks like stray text. You can dele
Having never looked at a schematic this way I wouldn't know what to
look for but from this excerpt can you tell if this is just a stray
refdes that doesn't belong? It is the only U9 found.
C 50600 46200 1 0 0 input-2.sym
{
T 50700 46200 5 10 1 1 0 0 1
net=_Clk
T 51200 46900
On Fri, Apr 29, 2011 at 2:30 PM, Rob Butts wrote:
> After entering a schematic and autonumbering it I have what seems to be
> an extra refdes text in the schematic that doesn't have a symbol that
> it goes with. I suspect it is from another symbol that I deleted that
> the refdes might ha
After entering a schematic and autonumbering it I have what seems to be
an extra refdes text in the schematic that doesn't have a symbol that
it goes with. I suspect it is from another symbol that I deleted that
the refdes might have been separated while dragging and dropping
compon
On Sun, 2011-03-20 at 10:17 -0400, Rob Butts wrote:
> I have a small circle in a symbol that I would like to fill in green
>and make a dot. How do I do this?
Make a circle, then use "ef" or "Edit -> Fill type", then select fill
type "Filled".
--
Peter Clifton
Electrical Engineering Divisio
I have a small circle in a symbol that I would like to fill in green
and make a dot. How do I do this?
Thanks
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Peter Clifton wrote:
> I'm not sure if the code would ignore the vias if you put the polygon on
> an "outline" or "route" layer.
It is true, there are no vias in the gerber file of the outline layer.
---<)kaimartin(>---
--
Kai-Martin Knaak
Email: k...@familieknaak.de
Öffentlicher PGP-Schlüssel:
On Thu, 2011-02-10 at 10:44 -0500, DJ Delorie wrote:
> > I want to define a zone for gold plating. If I put a polygon on a layer
> > it makes the layer included in all the vias.
> >
> > How do I make it not create via circles on this extra layer I defined?
>
> The only solution for these types o
> I want to define a zone for gold plating. If I put a polygon on a layer
> it makes the layer included in all the vias.
>
> How do I make it not create via circles on this extra layer I defined?
The only solution for these types of question is: hack pcb. Sorry.
_
I want to define a zone for gold plating. If I put a polygon on a layer
it makes the layer included in all the vias.
How do I make it not create via circles on this extra layer I defined?
Or, how to define a layer that doesn't get via circles?
John Griessen
_
william estrada wrote:
>Where can I find the definition of the attributes used to define a
> box in the sym files?
> Ex "B 300 0 1400 2500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1"
>
http://geda.seul.org/wiki/geda:file_format_spec#box
The first place to look for documentation on geda applica
Hi group,
Where can I find the definition of the attributes used to define a
box in the sym files?
Ex "B 300 0 1400 2500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1"
Thanks for your time.
--
William Estrada
Mt Umunhum, CA, USA
HTTP://64.124.13.3 ( Mt-Umunhum-Wireless.net )
Skype: MrUmunhum
__
On Wed, 5 Jan 2011 10:00:24 -0800
Colin D Bennett wrote:
> [...]
>
> Actually, I am impressed with the flexibility of your footgen.py
> script. It looks like you've created many different types of
> footprints using it.
I think we miss-understood each other. Or let me say I wasn't clear eno
On Wed, 29 Dec 2010 12:45:14 +0100
Levente Kovacs wrote:
> On Wed, 22 Dec 2010 17:29:24 -0800
> Colin D Bennett wrote:
>
> > You are not alone. Making footprints in pcb takes a lot of
> > practice, for me a least. I have made many footprints in pcb over
> > the past couple of years and still
On Wed, 22 Dec 2010 17:29:24 -0800
Colin D Bennett wrote:
> You are not alone. Making footprints in pcb takes a lot of practice,
> for me a least. I have made many footprints in pcb over the past
> couple of years and still I have to refer to guidelines, if I haven't
> made a footprint for some
On Wed, 22 Dec 2010 13:34:31 -0800
blueeag...@gmail.com wrote:
> I really like the gSchema program and after getting used to it, I
> find it better than most I have tried. But the PCB program has a lot
> to be desired. I could probably do it if all I needed was through
> hole, but I need some cu
blueeag...@gmail.com wrote:
> I really like the gSchema program and after getting used to it, I find it
> better than most I have tried. But the PCB program has a lot to be
> desired.
After getting used to it, I found pcb better than most I had tried :-)
> One
> thing that confuses me is why t
Stefan Salewski wrote:
> You can draw footprints in PCB program, it it described somewhere.
>
see:
http://geda.seul.org/wiki/geda:pcb_tips?&#how_do_i_edit_change_an_existing_footprint
Yes, the loss of information when converting a footprint to element
and back, makes the process a bit tedious. I
blueeag...@gmail.com writes:
> I really like the gSchema program and after getting used to it, I find it
> better than most I have tried. But the PCB program has a lot to be
> desired. I could probably do it if all I needed was through hole, but I
> need some custom parts. I could use KCAD I gu
On Wed, 2010-12-22 at 13:34 -0800, blueeag...@gmail.com wrote:
>I was wondering if someone could give me a good step by step on how to
>make a foot print.
Many footprints are available, some shipped with PCB, some at
gedasymbols.org, some at
http://www.luciani.org/geda/pcb/pcb-footprint-l
http://www.delorie.com/pcb/docs/gs/
Coordinates in footprints are relative to the footprint's "mark", or
relative origin. The mark is indicated by the diamond. I.e. you don't
move the diamond, you move everything else relative to the diamond :-)
If you select stuff and move it, only the select
I really like the gSchema program and after getting used to it, I find
it better than most I have tried. But the PCB program has a lot to be
desired. I could probably do it if all I needed was through hole, but
I need some custom parts. I could use KCAD I guess, but I would really
Den 2010-12-22 20:50:56 skrev DJ Delorie :
The default folder is the current working directory. If you're using
the desktop to start gschem, you should be able to tell the desktop icon
what it's starting directory is. If you start gschem from the terminal
the default folder is the current dir
The default folder is the current working directory. If you're using
the desktop to start gschem, you should be able to tell the desktop icon
what it's starting directory is. If you start gschem from the terminal
the default folder is the current directory inside the terminal.
It seems like the default folder is ${HOME} by default, how can I change
that? I couldn't find anything like ”settings” or ”preferences” in the
menues.
--
Kind regards
Johnny Rosenberg
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Stefan Salewski writes:
> What I wanted to say was: "Move to current Layer" makes not much sense
> for footprints, because we can have inner layers,
it does make sense, sometimes ...
> but we can not move footprints to that layers.
... pity
--
Stephan
_
Looking at your screen shot I'd say that J2 is on the solder side
(so it's greyed), while J1 and the brown traces are on component side
- that's why the trace does not connect to J2 while it appears to overlap.
The rat line on the overlapping pin is not a dot, probably because it
connects to the f
Am 17.10.2010 um 17:44 schrieb Stefan Salewski:
solder x
GND-solder x
VCC-solder x
comonent x
GND-component x
Vcc-component x
unused
unused
(bottom) x
(top) x
I set up layers stack when I start a new layout, but I think it will
work if you change
kai-martin knaak wrote:
Markus Hitter wrote:
http://github.com/Traumflug/Generation_7_Electronics
Somehow your layer stack got whacky. None of the actual layers are on
the "solder_side" or on the "component_side". These sides denote the
top copper layer and the bottom copper layer. Pins ar
On Sun, 2010-10-17 at 18:31 +0200, Karl Hammar wrote:
> Stefan Salewski:
> > On Sun, 2010-10-17 at 15:35 +0200, Karl Hammar wrote:
> > > There is also under "Edit->Move to current Layer M", but I haven't
> > > been able to move a footprint to the solder layer with that.
> > Of course you can not
Stefan Salewski:
> On Sun, 2010-10-17 at 15:35 +0200, Karl Hammar wrote:
> > There is also under "Edit->Move to current Layer M", but I haven't
> > been able to move a footprint to the solder layer with that.
> Of course you can not move it to inner layers, so Move to current Layer
> makes not mu
Markus Hitter wrote:
> http://github.com/Traumflug/Generation_7_Electronics
Somehow your layer stack got whacky. None of the actual layers are on
the "solder_side" or on the "component_side". These sides denote the
top copper layer and the bottom copper layer. Pins are ok with this.
But SMD-P
On Sun, 2010-10-17 at 17:20 +0200, Stefan Salewski wrote:
> My initial guess: Your traces are not in the top and bottom groups, so
Use the layers dialog, and make it similar as tut1.pcb for two layer
layout.
solder x
GND-solder x
VCC-solder x
comonent x
GND-component
On Sun, 2010-10-17 at 16:54 +0200, Markus Hitter wrote:
> Am 17.10.2010 um 16:25 schrieb gene glick:
>
> > If you are willing, send the .pcb file over. I can take a closer
> > look.
>
> That would be greatly appreciated! Schematics and the board with the
> 2-pin jumpers are on Github, it's t
Am 17.10.2010 um 16:25 schrieb gene glick:
If you are willing, send the .pcb file over. I can take a closer
look.
That would be greatly appreciated! Schematics and the board with the
2-pin jumpers are on Github, it's the Gen7Board.xxx:
http://github.com/Traumflug/Generation_7_Electronic
Am 17.10.2010 um 16:17 schrieb gene glick:
ElementLine [ ...
is that a typo?
It's an intentional cut to keep the message short. There are further
ElementLines.
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On Sun, 2010-10-17 at 16:20 +0200, Markus Hitter wrote:
>
> The problem is, an overlap between a pad and a track isn't recognized
> as a connection.
That would make sense if your dark red traces are on an inner layer.
As gene glick wrote, you may send a board for investigation.
If you are willing, send the .pcb file over. I can take a closer look.
gene
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Am 17.10.2010 um 15:47 schrieb Stefan Salewski:
On Sun, 2010-10-17 at 14:50 +0200, Markus Hitter wrote:
Hello all,
yesterday I tried to replace a number of 2-pin jumpers (footprint
JUMPER2) with solder jumpers.
Of course, this should work fine, it does for me.
gsch2pcb removes the old footp
ElementLine [ ...
is that a typo? The line is incomplete. I deleted, and then loaded the
part onto a layout, which worked out.
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Markus Hitter wrote:
Instead I even get DRC errors stating the track and the pad are too
close *sigh*
Maybe your design rules are prohibiting making the connection? You
could try disabling the "auto enforce drc clearance" - look under the
"settings" menu selections. If that works out, you
On Sun, 2010-10-17 at 15:47 +0200, Stefan Salewski wrote:
> For replacing footprints there is a special mode which allows you to
> replace single footprints -- sorry can not remember currently.
>
It is "Load element data to paste buffer", and now SHIFT LEFT MOUSE
CLICK over old elements. That wi
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