Re: gEDA-user: Icarus verilog Synthesis

I am looking for a book that for example describes how a for/while/repeat/forever and other verilog behavioral constructs are converted to multiplexors/and gates etc. For FPGA work, I am unaware of any engine that can synthesize those constructs. If you read through the XST manual

Re: gEDA-user: Icarus verilog Synthesis

Hi, Does any one know about any book that describes how to convert a behavioral code into unoptimized gate level netlist. I know that after an unoptimized gate level netlist is got logic synthesis is applied to get an optimized netlist. I have a book called Algorithms

Re: gEDA-user: Icarus verilog Synthesis

Am 04.09.2010 06:19, schrieb Ronald Mathias: I transform the Verilog code containing behavioral statements into verilog code that contains only gate level instantiations. This is passed as input to ABC Logic synthesis tool. Finally the output generated by ABC is passed to

Re: gEDA-user: Icarus verilog Synthesis

Hi, Thanks a lot. Regards Ronald Mathias On 9/4/10, Philipp Klaus Krause [1]...@spth.de wrote: Am 04.09.2010 06:19, schrieb Ronald Mathias: I transform the Verilog code containing behavioral statements into verilog code that contains

Re: gEDA-user: Icarus verilog Synthesis

What are you trying to do? Are you really trying to synthesize your Verilog design, meaning you are trying to generate a bit stream to load into your FPGA? Or are you trying to compile and simulate your Verilog? Icarus Verilog is mostly a *simulator*, not a synthesizer. There were some synthesis

gEDA-user: Icarus verilog Synthesis

Hi, I have written a verilog code that makes use of a user defined task to do some computation. The task takes two parameters as input and one parameter as output. When I try to synthesize it, I get the following error: internal error: NetProc::nex_output not implemented