I think grefdes is what I remembered reading about. I have now tried it
and in general, it does a nice job. Now I need to learn some Perl to
understand it better. It does not seem to understand about schematic
hierarchy however. It renames/renumbers even refdes names for the
hierarchy
When creating a hierarchy you end up with refdes numbers with the top
level refdes of the circuit symbol, a slash, and then the underlying
refdes such as X101/R102. I would like to end up with refdes on the top
level of R1, R2, etc. and parts from the underlying schematic be R101,
R102,
Steven Taylor wrote:
I would like to end up with refdes on the top
level of R1, R2, etc. and parts from the underlying schematic be R101,
R102, etc. for the first instance and R201, R202, etc. from the second
instance, and so on.
grefdes --pgskip 100 subschem1 subschem2 subschem3 subschem4
On Mon, 25 Feb 2008 10:05:01 -0600, John Griessen wrote:
grefdes --pgskip 100 subschem1 subschem2 subschem3 subschem4
I think this won't solve the problem. The OP said, he has multiple
instances of a subsheet under a main sheet. So he needs a script that
acts on the netlist rather than on the
Kai-Martin Knaak wrote:
On Mon, 25 Feb 2008 10:05:01 -0600, John Griessen wrote:
grefdes --pgskip 100 subschem1 subschem2 subschem3 subschem4
he has multiple
instances of a subsheet under a main sheet. So he needs a script that
acts on the netlist rather than on the schematics.
Oh...
Yes, exactly. I thought I had seen something about someone else having
done this before. There was something about changing the refdes from the
composite sheet/part style into a flat numbering system. Maybe I'm just
dreaming. Anyway, I'll take a look at grefdes tomorrow and see what I can
I really don't like loosing the hierarchy information.
It would be nice if you could just get pcb to put the refdes without the
hierarchy string into the silkscreen. The hierarchy info I build into
the silkscreen by drawing boxes around each section and adding the
hierarchy string as text inside
On Mon, 11 Feb 2008 16:55:51 -0600, John Griessen wrote:
Want me to create a schematic set with embedded symbols and send it to
you for another example to follow?
Can you post it to this list too?
---(kaimartin)---
--
Kai-Martin Knaak tel: +49-511-762-2895
I had put the source= attribute in the symbol for the underlying
schematic page. That was enough for the proper hierarchy operations except
for the drc and netlist generation. As per John's sample schematics, I
added a source= attribute on each of the instantiated symbols at the top
level
My symbol, that I created, that represents my lower level schematic has
pins with only pin numbers, pinseq numbers, and pin labels. The pin labels
match the refdes on the IO connectors on the underlying schematic. That is
the way it was done on the gTAG example. I tried assigning pintypes to
The net list comes out OK except for two of the nets which don't connect
through between the upper level and the lower level schematics.
Steve
On Mon, 11 Feb 2008 13:09:40 -0800, Peter Clifton [EMAIL PROTECTED] wrote:
On Mon, 2008-02-11 at 13:07 -0800, Steve Taylor wrote:
I am evidently
On Mon, 2008-02-11 at 13:07 -0800, Steve Taylor wrote:
I am evidently doing something wrong and I need some help in pointing me
in the right direction.
It might be that the drc2 backend doesn't support this very well. Does
the netlist look OK when you netlist for the circuit layout software
I an a new user of gEDA and have completed one single level schematic and
am working on a second schematic. This second one has a top level page
with a lower level section repeated four times. After a lot of reading on
the web, looking at the examples, and experimentation, I have created the
Steven Taylor wrote:
My symbol, that I created, that represents my lower level schematic has
pins with only pin numbers, pinseq numbers, and pin labels. The pin labels
match the refdes on the IO connectors on the underlying schematic.
OK, How about the refdes of the symbol that corresponds
Continuing my checking, I have found that *all* the nets on the lower
level schematics are showing up in the net list file twice, first as
separate nets and then again as included in the proper nets with all the
pins from the lower levels combined with the top level connections. The
reason
Actually, I have to take that back, the nets do show up correctly
connected for all of the IOs, but the pins on the lower level schematic
also show up in the net list as nets with only a single pin. So those nets
in question are actually in the net list twice, once as single pin nets
and
Steve Taylor wrote:
When I run the same command on the top level schematic, I get a long list
of Duplicated references for every symbol in the underlying schematic, I
get another list for duplicate slot 1 of every symbol, and I get errors on
three of my inputs, listing the components to
Yes, John, that would be helpful. It would give me a second sample to try
here and see where I may be going wrong.
Thanks,
Steve
Want me to create a schematic set with embedded symbols and send it to
you for another example to follow?
The schematic is for some free-published hardware...
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