Timothy Normand Miller wrote:
Sorry about the cross-post. We're -- THIS close to getting OGD1
done, with artwork in the hands of board makers who are working on
quotes, and we've discovered a problem that could make the video
output unacceptable.
We've discovered that the clock generators
BTW, I just wanted to thank everyone for the help with the clock
generation problem. Lots of useful information!
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Random ideas: try better supply decoupling or package, stop other FPGA
outputs when the clock generator is active (or at least put them far
from the generator outputs). Check PCB - especially for return current
paths of noisy signals.
-r.
On Nov 28, 2007 7:09 PM, Timothy Normand Miller [EMAIL
Sorry about the cross-post. We're -- THIS close to getting OGD1
done, with artwork in the hands of board makers who are working on
quotes, and we've discovered a problem that could make the video
output unacceptable.
We've discovered that the clock generators in the Xilinx FPGA part are
lousy
Hello Timothy,
take a look at Analog Devices AD9516-0 ... 5 family, these are flexible clock
generators with many outputs and low jitter performance, as far as i understood
in
the femti-seconds range ( 1ps jitter). I have no practical experience with
them but i plan to use them in a new
Timothy -
On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote:
We've discovered that the clock generators in the Xilinx FPGA part are
lousy for generating video clocks.
Welcome to the club.
So the best solution we can come up with is to put on some external
clock
On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote:
We've discovered that the clock generators in the Xilinx FPGA part are
lousy for generating video clocks.
DCMs have lousy jitter, yes. Altera parts have real PLLs, though.
which causes artifacts on DVI monitors at
Ben -
On Wed, Nov 28, 2007 at 12:49:50PM -0800, Ben Jackson wrote:
On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller wrote:
We've discovered that the clock generators in the Xilinx FPGA part are
lousy for generating video clocks.
DCMs have lousy jitter, yes. Altera
On Wed, Nov 28, 2007 at 01:02:00PM -0800, Larry Doolittle wrote:
DCMs have lousy jitter, yes. Altera parts have real PLLs, though.
Even if the FPGA chip were perfect, there are so many digital signals
flying around the package that ground bounce alone will kill any semblance
of low
On Nov 28, 2007, at 4:02 PM, Larry Doolittle wrote:
That's kind of surprising, because the DVI spec has a bitrate 10x the
fundamental clock, so both the transmitter and receiver generally have
to have PLLs.
Just the receiver, right? And that cable length comment makes me
suspicious
On Nov 28, 2007 11:09 AM, Timothy Normand Miller [EMAIL PROTECTED] wrote:
Does anyone know anything about these? Do you have experience with
specific high-frequency clock generators and know how they perform and
what kind of jitter they produce?
These are kind of like those four pin crystal
On Nov 28, 2007, at 1:49 PM, Ben Jackson wrote:
On Wed, Nov 28, 2007 at 02:09:22PM -0500, Timothy Normand Miller
wrote:
We've discovered that the clock generators in the Xilinx FPGA part
are
lousy for generating video clocks.
DCMs have lousy jitter, yes.
Indeed. The Spartan 3E claims
12 matches
Mail list logo
