al davis wrote:
On Tuesday 23 February 2010, John Griessen wrote:
Would you still use gschem/gnetlist to schematically connect
verilog modules? That depends on having a good translator
first, right?
Anything that generates a netlist.
Gnucap uses language plugins to read whatever input
al davis wrote:
I proposed a translator system, using an intermediate language,
to translate both ways between schematic, layout, and
simulation. It needs to happen.
I've got a phone call to Reid Wenders of Triad scheduled this PM.
Anyone have any ideas you'd like mentioned to him?
I have daydreamed about the possibility of linking gEDA with qucs and
simavr/gdb for example. To be able to create a circuit layout and
perform harmonic ballance simulation combined with microcontroller
code simulation... Oh, and while I daydream, an integrated tool for
doing FEM analysis the pcb
On Wed, 2010-02-24 at 09:46 +1100, Geoff Swan wrote:
I have daydreamed about the possibility of linking gEDA with qucs and
simavr/gdb for example. To be able to create a circuit layout and
perform harmonic ballance simulation combined with microcontroller
code simulation... Oh, and while I
On Tuesday 23 February 2010, John Griessen wrote:
Anyone have any ideas you'd like mentioned to him? Questions
I should ask? I'm just planning on telling him the status of
verilog-ams backend of gnetlist and that it can run some
simulations from a netlist -- the way it needs to be for
Peter Clifton wrote:
On Wed, 2010-02-24 at 09:46 +1100, Geoff Swan wrote:
I have daydreamed about the possibility of linking gEDA with qucs and
simavr/gdb for example.
My phone conversation today with Mr Wender of Triad was about verilog-ams and
the
possibilities it offers mostly. One way
On Tuesday 23 February 2010, John Griessen wrote:
Al, are you saying that Icarus verilog would run along side
of gnucap once that interface is ready?
Icarus has two key parts .. A compiler, and a virtual machine.
In its normal use, the compiler generates code for the virtual
machine, then
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