On Sat, 05 Apr 2008 09:28:43 -0500
John Griessen [EMAIL PROTECTED] wrote:
Levente wrote:
http://web.interware.hu/lekovacs/reflow_oven/index.html
Actually, it is an electric heater. The problem is that the heat exchange
is slow, and it can't maintain the slopes coming from the heat
On Sat, 29 Mar 2008 09:19:50 -0500
John Griessen [EMAIL PROTECTED] wrote:
Steve Meier wrote:
An interesting hobbyist project might be to modify a hot plate to be
computer controlled with a thermal couple feed back loop to meet
Altera's requirements.
Levente has a design for a toaster
Levente wrote:
http://web.interware.hu/lekovacs/reflow_oven/index.html
Actually, it is an electric heater. The problem is that the heat exchange is
slow, and it can't maintain the slopes coming from the heat profile. I use a
PT100 thermo-sensor mounted on a pice of PCB (not the PCB being
Steve Meier wrote:
Isn't the switch to rohs soldering a bigger issue?
There's a rumor that there is a RoHS exception for package leg pitches of 0.5mm
and under,
meaning all you do to get exemption is put such a part on your board...
There's an email list of people documenting soldering
Steve Meier wrote:
An interesting hobbyist project might be to modify a hot plate to be
computer controlled with a thermal couple feed back loop to meet
Altera's requirements.
Levente has a design for a toaster controller I think he'll share.
John Griessen
--
Ecosensory Austin TX
Hallo.
Am 28.03.2008 um 06:51 schrieb Jesse Gordon:
Can you please tell me a little more about meta-FPGA? I have no idea
what it means, but I was talking with someone (who knows slightly more
about fpgas then I, which still isn't much) a while back the general
idea of constructing an fpga
High speed memory is now staggering the transmission of each data line
to minimize cross talk. High end fpga's can support qdr II memory
devices to clock speeds of over 500 MHz. The qdr ii has two data buses
one for read and one for writing. Each bus supports a transfer on each
edge of the clock.
On Mar 28, 2008, at 10:10 AM, Steve Meier wrote:
High speed memory is now staggering the transmission of each data line
to minimize cross talk. High end fpga's can support qdr II memory
devices to clock speeds of over 500 MHz. The qdr ii has two data buses
one for read and one for writing.
Jesse Gordon wrote:
Igor2 wrote:
If we are at tools, I wonder... Is there an FPGA family that I could use
without using non-free software at all?
Google Slipway. The author says it's not quite ready for building things
that are needing reliability and he's busy on a contract job, so it's a
Larry Doolittle wrote:
Also as a curiosity, see Reinoud's MPGA, an open source meta-FPGA.
That one seems to have dropped off the 'net. Does anyone have an
archived copy?
I may. I'lll rummage on my hard drive. I liked that concept.
You could take a normal FPGA and develop one meta layer
Hagen SANKOWSKI wrote:
I think the patent issue is a bigger show stopper. Here we are
stepping in the field of real hardware, there are a lot of more
patents than software developer may thinking off. I did a lot
investigation in the fpga topic - and still dream of a free one!
FPGAs are now
6/6 is doable if you slightly cheat the size of the solder pads.
The problem is the vias - a 12 mil hole with 6 mil rules is a 24 mil
via pad, with only 39 mil on center (1mm) that leaves 15 mil between
vias, which is enough for a 5/5 trace but not a 6/6 trace.
So with 6/6 rules, you're
I have routed a 900 pin bga 1mm pitch on 4 signal layers.
30x30
using Larry's math
30/2 - 2 = 13 layers this seems pessimistic.
for details see
http://archives.seul.org/geda/user/Jan-2005/msg00196.html
Steve M.
On Thu, 2008-03-27 at 17:21 -0700, Larry Doolittle wrote:
Guys -
On
ah it assumes all pins are io and that you can only get one trace
between rows?
Realistically, the center pins are power and ground with io allong the
edges.
so lets say for a row the center half of the pins are power and ground
and you can get two traces between rows.
max signal layers = (n/2
Again pessimistic.
max signal layers = (n/2 - 2) / 2 / 2
the last / 2 says I get to work of of each edge of the device.
So I should have been able to route a 900 pin fpga on 4 layers. at least
as far as clearing the fpga.
If we don't use via in pads we loose the two outer layers for routing to
Cheating? I did that board when pcb only
I meant that hobby folks can rarely afford to have via-in-pad done.
Unless there's some way to hand-prep each via so the bga can be
soldered on. Otherwise, we need to either stick with normal rules
or avoid BGAs altogether.
The real issue here
Steve -
On Fri, Mar 28, 2008 at 10:27:28AM -0700, Steve Meier wrote:
On Fri, 2008-03-28 at 10:20 -0700, Larry Doolittle wrote:
OK. Just be sure to give the FPGA direct access (via PHY) to
Ethernet. The same concept also applies to network performance.
I'd venture to say you want four
Cheating? I did that board when pcb only supported 8 layers so yep lie
steal cheat grand larceny I did what ever I could to make it fit ;) And
I am still thrilled that the difference between detection on the analog
channels was less then 10 pico seconds. Far below what we could directly
measure on
My understanding is that the backside of the via hole pattern is filled
with an epoxy which prevents the chimney effect (heat rising through the
via and sucking/wicking the solder down into the via). I think that
should be doable by a hobbyist.
Isn't the switch to rohs soldering a bigger issue?
Isn't the switch to rohs soldering a bigger issue?
As in we don't have to ? :-)
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Well not yet at least not here in the US how about our European friends
though?
On Fri, 2008-03-28 at 16:26 -0400, DJ Delorie wrote:
Isn't the switch to rohs soldering a bigger issue?
As in we don't have to ? :-)
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Also, even we in the US won't be able to get leaded bga's for ever.
On Fri, 2008-03-28 at 16:26 -0400, DJ Delorie wrote:
Isn't the switch to rohs soldering a bigger issue?
As in we don't have to ? :-)
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Well not yet at least not here in the US how about our European
friends though?
I was thinking more of hobbyists have less restrictions than
commercial as far as ROHS goes. At least, that's if we can *get*
non-ROHS parts. I don't mind ROHS parts as long as I can use 63/37
solder.
I have seen rohs bga's where the balls have been removed and reballed
with leaded balls. Seems like a risky extra step to avoid the
temperature requirements. How hot does your hot plate get?
Steve M.
On Fri, 2008-03-28 at 16:34 -0400, DJ Delorie wrote:
Well not yet at least not here in the US
I have seen rohs bga's where the balls have been removed and
reballed with leaded balls. Seems like a risky extra step to avoid
the temperature requirements. How hot does your hot plate get?
Hot enough, I think. I haven't had a chance to see how hot it gets -
I just remove the board once the
An interesting hobbyist project might be to modify a hot plate to be
computer controlled with a thermal couple feed back loop to meet
Altera's requirements.
I've been thinking of having a friend machine off the cast iron top
half and bolt on an aluminum disk, so that it heats faster and more
On Fri, 28 Mar 2008 13:28:22 -0700, Steve Meier wrote:
Well not yet at least not here in the US how about our European friends
though?
It took me quite a while to find a decent non-lead solder that produces
smooth reliable connections when hand soldered. Standard SAC sucks. The
guys at
ATX motherboard (or any pc motherboard shape, really, like micro-atx
or some laptop). PCI/PCIe slots, ISA slots, standard connectors,
SDRAM - whatever.
A huge FPGA in the middle.
Or two or three big QFP ones.
100% synthetic circuitry, including a soft CPU, in a PC case.
If it's designed for
DJ Delorie [EMAIL PROTECTED] wrote:
ATX motherboard (or any pc motherboard shape, really, like micro-atx
or some laptop). PCI/PCIe slots, ISA slots, standard connectors,
SDRAM - whatever.
A huge FPGA in the middle.
Or two or three big QFP ones.
100% synthetic circuitry, including a
On Thu, Mar 27, 2008 at 06:36:38PM -0400, DJ Delorie wrote:
ATX motherboard (or any pc motherboard shape, really, like micro-atx
or some laptop). PCI/PCIe slots, ISA slots, standard connectors,
SDRAM - whatever.
A huge FPGA in the middle.
[...]
My understanding is that with the GHz
On Thu, Mar 27, 2008 at 5:36 PM, DJ Delorie [EMAIL PROTECTED] wrote:
ATX motherboard (or any pc motherboard shape, really, like micro-atx
or some laptop). PCI/PCIe slots, ISA slots, standard connectors,
SDRAM - whatever.
A huge FPGA in the middle.
Or two or three big QFP ones.
My understanding is that with the GHz busses on modern mobos you need
With a soft CPU, the busses can go slower. I wouldn't expect such a
project to compete with PCs.
I thought it was basically impossible to get it right without
assistance from the CAD tool.
Well, we can change the CAD
http://geekz.co.uk/lovesraymond/archive/taking-freedom-further
Yeah, that fits.
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DJ Delorie wrote:
http://www.xilinx.com/products/boards/ml410/index.html
They have a lot of support chips on that board, though. Like the
south bridge, CF controller, PCI bridge, etc. I was thinking more
like every connector goes directly to an FPGA pin. Maybe one fpga
for the cpu
Guys -
On Thu, Mar 27, 2008 at 04:22:34PM -0700, Jesse Gordon wrote:
DJ Delorie wrote:
http://www.xilinx.com/products/boards/ml410/index.html
They have a lot of support chips on that board, though. Like the
south bridge, CF controller, PCI bridge, etc. I was thinking more
like every
1. Self-reconfigurable FPGAs have been promised for years, but aren't
ready, and probably never will be. Think carefully about the boot
sequence, and how one FPGA can boot the next. Having more than one
FPGA is probably a good thing.
What about the new flash-based FPGAs? Maybe not as big,
Randall Nortman wrote:
I thought it was
basically impossible to get it right without assistance from the CAD
tool.
PCIe keeps the signal lines differential and regular, so you have a chance.
The open graphics project is slowly moving along -- they are motivated by
several partners
that
Larry Doolittle [EMAIL PROTECTED] writes:
Assume 1mm pitch and 5/5 space/trace.
Turns out Sierra can do this, for a fee. A 7x7 4-layer board, with
5/5 rules and 12 mil holes, costs about $130ea qty5 if you don't mind
waiting for it. Of course, that's a $650 investment, and you still
have to
On Thu, Mar 27, 2008 at 09:28:23PM -0500, John Griessen wrote:
Larry Doolittle wrote:
Self-reconfigurable FPGAs have been promised for years, but aren't
ready, and probably never will be.
I guess that's because the fpga makers seem to not want to let out their
programming details --
On Thu, 27 Mar 2008, Larry Doolittle wrote:
On Thu, Mar 27, 2008 at 09:28:23PM -0500, John Griessen wrote:
Larry Doolittle wrote:
Self-reconfigurable FPGAs have been promised for years, but aren't
ready, and probably never will be.
I guess that's because the fpga makers seem to not want
Igor2 wrote:
If we are at tools, I wonder... Is there an FPGA family that I could use
without using non-free software at all?
I was going to ask that very question. The closest I've come to free
was xilinx's ISE Impact webpack which of course is only free to use and
only free for
Jesse -
On Thu, Mar 27, 2008 at 08:28:29PM -0700, Jesse Gordon wrote:
Igor2 wrote:
If we are at tools, I wonder... Is there an FPGA family that I could use
without using non-free software at all?
I was going to ask that very question. The closest I've come to free
was xilinx's ISE
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