Re: [gem5-dev] Review Request 2141: arm: Add support for ARMv8 (AArch64 & AArch32)

Thanks Ali for the response. That makes sense. However, I faced another issue that is weird. If I set *numPhysFloatRegs* to 160, I don't get any assertion error, but the simulation does not progress. I looked into this and I realized that this is because of lack of free physical registers. Even in

Re: [gem5-dev] Review Request 2141: arm: Add support for ARMv8 (AArch64 & AArch32)

> On June 30, 2014, 8:34 p.m., Amin Farmahini wrote: > > After applying this patch, the minimum number of float regs should be 160, > > even for ARMv7 ISA. If you set the number of numPhysFloatRegs to lower than > > 160, you get an assertion error from cpu/o3/cpu.cc: > > assert(params->numPhysF

Re: [gem5-dev] Review Request 2141: arm: Add support for ARMv8 (AArch64 & AArch32)

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2141/#review5169 --- After applying this patch, the minimum number of float regs should be 160

[gem5-dev] changeset in gem5: mem: Extend DRAM row bits from 16 to 32 for l...

changeset 70333502b9b5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=70333502b9b5 description: mem: Extend DRAM row bits from 16 to 32 for larger densities This patch extends the DRAM row bits to 32 to support larger density memories. Additional chec

[gem5-dev] changeset in gem5: mem: DRAMPower trace formatting script

changeset 72277952d444 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=72277952d444 description: mem: DRAMPower trace formatting script This patch adds a first version of a script that processes the debug output and generates a command trace for DRAMPo

[gem5-dev] changeset in gem5: mem: DRAMPower trace output

changeset 0ad233f0a77d in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=0ad233f0a77d description: mem: DRAMPower trace output This patch adds a DRAMPower flag to enable off-line DRAM power analysis using the DRAMPower tool. A new DRAMPower flag is added

[gem5-dev] changeset in gem5: power: Add basic DVFS support for gem5

changeset 6bbb7ae309ac in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=6bbb7ae309ac description: power: Add basic DVFS support for gem5 Adds DVFS capabilities to gem5, by allowing users to specify lists for frequencies and voltages in SrcClockDomains a

[gem5-dev] changeset in gem5: mem: Add bank and rank indices as fields to t...

changeset e0e3efe3b1d5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e0e3efe3b1d5 description: mem: Add bank and rank indices as fields to the DRAM bank This patch adds the index of the bank and rank as a field so that we can determine the identity o

[gem5-dev] changeset in gem5: cpu: implement a bi-mode branch predictor

changeset d2deb51a4abf in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d2deb51a4abf description: cpu: implement a bi-mode branch predictor diffstat: src/cpu/o3/fetch_impl.hh|4 +- src/cpu/pred/BranchPredictor.py |2 +- src/cpu/pred/SConscript

[gem5-dev] changeset in gem5: arm: make the bi-mode predictor the default f...

changeset cfb6b578a89a in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=cfb6b578a89a description: arm: make the bi-mode predictor the default for O3_ARM_v7a_BP the branch predictor used in the Cortex-A15 is a bi-mode style predictor, see: http