Re: [gem5-dev] Protocol Specific Profiling

I have more questions/issues on this topic of protocol specific profiling. I do not believe this issues should be fixed by having SLICC understand more STL types. I should have pointed out before that many times it is not one specific protocol that needs special profiling, but rather a set of

Re: [gem5-dev] changeset in gem5: ruby: slicc: change the way configurable memb...

Hi Nilay, Could you explain the motivation behind this change? What was wrong with the previous notation that data member declarations are separated by commas rather than semi-colons? This is the type of seemingly unnecessary change that make it difficult for users to stay in sync with the pu

Re: [gem5-dev] Review Request 2516: config: Add options to take/resume from SimPoint checkpoints

> On Nov. 25, 2014, 10:02 p.m., Nilay Vaish wrote: > > I suggest the additions being made to the Simulation.py file be made by > > creating new functions. > > I think the run function is already too big and confusing. I can work on cleaning up the patch by creating new functions as suggested.

Re: [gem5-dev] changeset in gem5: ruby: slicc: change the way configurable memb...

On Tue, 2 Dec 2014, Beckmann, Brad wrote: Hi Nilay, Could you explain the motivation behind this change? What was wrong with the previous notation that data member declarations are separated by commas rather than semi-colons? I think in most places in SLICC we use comma to separate the att

Re: [gem5-dev] [gem5-users] New ARM Full-System Files

Yes. The source repos used to make those kernels is the same as the source repos referenced here: http://gem5.org/ARM_Linux_Kernel Cheers, Anthony Gutierrez http://web.eecs.umich.edu/~atgutier On Tue, Dec 2, 2014 at 1:02 PM, Guru Prasad wrote: > Hi, > > Are the kernel sources also available? I

Re: [gem5-dev] Review Request 2541: sim: Make it possible to override the breakpoint length check.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2541/#review5605 --- Ship it! Ship It! - Nilay Vaish On Nov. 25, 2014, 11:47 a.m., Gabe Bl

Re: [gem5-dev] Review Request 2538: misc: Make the GDB register cache accessible in various sized chunks.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2538/#review5604 --- Ship it! Seems fine other than the one comment I have made below. src/

Re: [gem5-dev] Review Request 2528: config: make M5_PATH a real search path

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2528/#review5603 --- Ship it! Ship It! - Nilay Vaish On Nov. 24, 2014, 2:48 a.m., Steve Re

[gem5-dev] changeset in gem5: mem: Clean up packet data allocation

changeset c848de089432 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=c848de089432 description: mem: Clean up packet data allocation This patch attempts to make the rules for data allocation in the packet explicit, understandable, and easy to verify.

[gem5-dev] changeset in gem5: mem: Relax packet src/dest check and shift on...

changeset fc4c90a7d2f5 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=fc4c90a7d2f5 description: mem: Relax packet src/dest check and shift onus to crossbar This patch allows objects to get the src/dest of a packet even if it is not set to a valid port

[gem5-dev] changeset in gem5: mem: Assume all dynamic packet data is array ...

changeset c99c8d2a7c31 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=c99c8d2a7c31 description: mem: Assume all dynamic packet data is array allocated This patch simplifies how we deal with dynamically allocated data in the packet, always assuming tha

[gem5-dev] changeset in gem5: config: Fix to SystemC example's event handling

changeset 997be6ba467e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=997be6ba467e description: config: Fix to SystemC example's event handling This patch fixes checkpoint restore in the SystemC hosting example by handling early PollEvent events corr

[gem5-dev] changeset in gem5: arm: Fix TLB ignoring faults when table walking

changeset e622a3e2ed14 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e622a3e2ed14 description: arm: Fix TLB ignoring faults when table walking This patch fixes a case where the Minor CPU can deadlock due to the lack of a response to TLB request becau

[gem5-dev] changeset in gem5: mem: Support WriteInvalidate (again)

changeset d1e1e851 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d1e1e851 description: mem: Support WriteInvalidate (again) This patch takes a clean-slate approach to providing WriteInvalidate (write streaming, full cache line writes without

[gem5-dev] changeset in gem5: mem: Remove WriteInvalidate support

changeset c04dc66e4316 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=c04dc66e4316 description: mem: Remove WriteInvalidate support Prepare for a different implementation following in the next patch diffstat: src/mem/cache/base.hh |1 - src/mem/c

[gem5-dev] changeset in gem5: scons: Ensure dictionary iteration is sorted ...

changeset babb40bd2fc6 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=babb40bd2fc6 description: scons: Ensure dictionary iteration is sorted by key This patch adds sorting based on the SimObject name or parameter name for all situations where we itera

[gem5-dev] changeset in gem5: cpu: Fix retries on barrier/store in Minor's ...

changeset 7c4f1d0a8cff in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=7c4f1d0a8cff description: cpu: Fix retries on barrier/store in Minor's store buffer This patch fixes a case where a store in Minor's store buffer never leaves the store buffer as it

[gem5-dev] changeset in gem5: stats: Bump stats for fixes, mostly TLB and W...

changeset 1c9d5d9417b3 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=1c9d5d9417b3 description: stats: Bump stats for fixes, mostly TLB and WriteInvalidate diffstat: tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt | 1869 +- tes

[gem5-dev] changeset in gem5: mem: Use const pointers for port proxy write ...

changeset a8c16e2d466a in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=a8c16e2d466a description: mem: Use const pointers for port proxy write functions This patch changes the various write functions in the port proxies to use const pointers for all sou

[gem5-dev] changeset in gem5: mem: Make the requests carried by packets const

changeset ffd46545b284 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ffd46545b284 description: mem: Make the requests carried by packets const This adds a basic level of sanity checking to the packet by ensuring that a request is not modified once th

[gem5-dev] changeset in gem5: stats: Bump stats for o3 LSQ changes

changeset de2979ff873a in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=de2979ff873a description: stats: Bump stats for o3 LSQ changes diffstat: tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 1594 +- tests/long/fs/10.linux-boot/ref/ar

[gem5-dev] changeset in gem5: mem: Cleanup Packet::checkFunctional and hasD...

changeset dcb908e40547 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=dcb908e40547 description: mem: Cleanup Packet::checkFunctional and hasData usage This patch cleans up the use of hasData and checkFunctional in the packet. The hasData function is u

[gem5-dev] changeset in gem5: cpu: Move packet deallocation to recvTimingRe...

changeset 3b405d11d6dc in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=3b405d11d6dc description: cpu: Move packet deallocation to recvTimingResp in the O3 CPU Move the packet deallocations in the O3 CPU so that the completeDataAccess deals only with t

[gem5-dev] changeset in gem5: cpu, o3: Ignored invalidate causing same-addr...

changeset a8d612fa170b in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=a8d612fa170b description: cpu, o3: Ignored invalidate causing same-address load reordering In case the memory subsystem sends a combined response with invalidate (e.g. ReadRespWith

[gem5-dev] changeset in gem5: mem: Add a GDDR5 DRAM config

changeset e1a853349529 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e1a853349529 description: mem: Add a GDDR5 DRAM config This patch adds a first cut GDDR5 config to accommodate the users combining gem5 and GPUSim. The config is based on a SK Hynix

[gem5-dev] changeset in gem5: mem: Make Request getters const

changeset e70523bd0d26 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e70523bd0d26 description: mem: Make Request getters const This patch tidies up the Request class, making all getters const. The odd one out is incAccessDepth which is called by the

[gem5-dev] changeset in gem5: cpu: Always mask the snoop address when perfo...

changeset 95297ec0f14b in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=95297ec0f14b description: cpu: Always mask the snoop address when performing lock check Ensure the snoop address check is always using a cache-block aligned address. This patch upda

[gem5-dev] changeset in gem5: config: SystemC Gem5Control top level additions

changeset 5d7af9fa9809 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=5d7af9fa9809 description: config: SystemC Gem5Control top level additions This patch cleans up a few style issues and adds a few capabilities to the SystemC top level 'Gem5Control/

[gem5-dev] changeset in gem5: cpu: Fix memoryIssueLimit checking in Minor

changeset 953d7b741619 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=953d7b741619 description: cpu: Fix memoryIssueLimit checking in Minor This patch fixes the checking of the number of memory instructions issued per cycles in the Minor CPU. diffst

[gem5-dev] changeset in gem5: mem: Remove null-check bypassing in Packet::g...

changeset b99fdc295c34 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b99fdc295c34 description: mem: Remove null-check bypassing in Packet::getPtr This patch removes the parameter that enables bypassing the null check in the Packet::getPtr method. A n

[gem5-dev] changeset in gem5: mem: Add checks and explanation for assertMem...

changeset 926802ed1536 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=926802ed1536 description: mem: Add checks and explanation for assertMemInhibit usage diffstat: src/mem/cache/cache_impl.hh | 7 ++- src/mem/packet.hh | 7 ++- 2 files changed,

[gem5-dev] changeset in gem5: mem: Remove redundant Packet::allocate calls

changeset 23593fdaadcd in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=23593fdaadcd description: mem: Remove redundant Packet::allocate calls This patch cleans up the packet memory allocation confusion. The data is always allocated at the requesting si

[gem5-dev] changeset in gem5: mem: Add const getters for write packet data

changeset 755b18321206 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=755b18321206 description: mem: Add const getters for write packet data This patch takes a first step in tightening up how we use the data pointer in write packets. A const getter is

Re: [gem5-dev] Syscall emulation/fake Linux/KVM/SE FS integration

X86LinuxSESystem is a better name. Gabe On Mon, Dec 1, 2014 at 3:05 AM, Gabe Black wrote: > One of the last things I did the last time I was working on gem5 was to > merge the SE and FS builds of the simulator into one. I didn't really > finish it before I left, though, and in a lot of ways it'

[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple