[gem5-dev] changeset in gem5: misc: Generalize GDB single stepping.

changeset 6efb37480d87 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=6efb37480d87 description: misc: Generalize GDB single stepping. The new single stepping implementation for x86 doesn't rely on any ISA specific properties or functionality. This cha

[gem5-dev] changeset in gem5: x86: Implement a remote GDB stub.

changeset e60c7758cf69 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e60c7758cf69 description: x86: Implement a remote GDB stub. This stub should allow remote debugging of 32 bit and 64 bit targets. Single stepping seems to work, as do breakpoints.

[gem5-dev] changeset in gem5: misc: Add some utility functions for schedule...

changeset 910fc5624d68 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=910fc5624d68 description: misc: Add some utility functions for schedule inst commit events. These can be used to simplify the implementation of single step in derived classes. dif

[gem5-dev] changeset in gem5: misc: Rename the GDB "Event" event class to I...

changeset 3d7653a2538b in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=3d7653a2538b description: misc: Rename the GDB "Event" event class to InputEvent. The "Event" name is the same as the base event class. That's a bit confusing, and makes it a littl

[gem5-dev] Ruby and O3 model assertion failure

Hi everyone, There seems to be an assertion failure if O3 cpu model is ran with ruby memory model: 444500: system.cpu.iew.lsq.thread0: Executing load PC (0x4cd4ea=>0x4cd4f1).(1=>2), [sn:146] 444500: system.cpu.iew.lsq.thread0: Read called, load idx: 12, store idx: 20, storeHead: 12 addr: 0x1

Re: [gem5-dev] Review Request 2542: x86: Implement a remote GDB stub.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2542/#review5651 --- Ship it! Ship It! - Steve Reinhardt On Dec. 5, 2014, 2:46 a.m., Gabe

Re: [gem5-dev] Review Request 2556: misc: Generalize GDB single stepping.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2556/#review5650 --- Ship it! Agreed, I'm a big fan of patches that are a net reduction in LO

Re: [gem5-dev] Review Request 2555: misc: Add some utility functions for schedule inst commit events.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2555/#review5649 --- Ship it! Ship It! - Steve Reinhardt On Dec. 5, 2014, 2:36 a.m., Gabe

Re: [gem5-dev] Review Request 2554: misc: Rename the GDB "Event" event class to InputEvent.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2554/#review5648 --- Ship it! Ship It! - Steve Reinhardt On Dec. 5, 2014, 2 a.m., Gabe Bla

Re: [gem5-dev] Review Request 2548: arm: Add unlinkat syscall implementation

> On Dec. 4, 2014, 7:03 a.m., Nilay Vaish wrote: > > src/sim/syscall_emul.hh, line 201 > > > > > > How will the compiler choose between the two versions of unlinkFunc? I > > think we should either drop the default argument

Re: [gem5-dev] Review Request 2548: arm: Add unlinkat syscall implementation

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2548/#review5646 --- Ship it! Ship It! - Steve Reinhardt On Dec. 4, 2014, 5:14 p.m., mike

Re: [gem5-dev] Review Request 2553: dev: Prevent intel 8254 timer events firing before startup

> On Dec. 5, 2014, 11:45 a.m., Andreas Hansson wrote: > > Look good to me. Do the regressions still pass? I ran the same tests as I mentioned in r/2545. Please let me know if I need to test more. - Cagdas --- This is an automatically g

Re: [gem5-dev] Review Request 2545: dev: Prevent MC146818 timer RTC events firing before startup

> On Dec. 5, 2014, 11:47 a.m., Andreas Hansson wrote: > > Looks good. What about the regressions? I have run hello world in se mode for both X86 and ARM. I also have a small program that does int array manipulation, and I run it in se mode for both X86 and ARM. I typically run timing and detai

Re: [gem5-dev] ARM DVFS : all the cores are not online when performing ARM full system simulation to test DVFS

Lokesh, from your config.ini and config.pdf, I see that you are only initialising a *single* core. Can you please double check that you initialise the right number of cores in your configuration files and retry? -- Many thanks, Stephan Stephan Diestelhorst Staff Engineer ARM R&D Systems On

Re: [gem5-dev] Review Request 2545: dev: Prevent MC146818 timer RTC events firing before startup

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2545/#review5643 --- Ship it! Looks good. What about the regressions? - Andreas Hansson On

Re: [gem5-dev] Review Request 2553: dev: Prevent intel 8254 timer events firing before startup

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2553/#review5642 --- Ship it! Look good to me. Do the regressions still pass? - Andreas Hans

Re: [gem5-dev] Review Request 2556: misc: Generalize GDB single stepping.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2556/#review5641 --- Ship it! looks like a substantial improvement... visually seems fine but

Re: [gem5-dev] Review Request 2555: misc: Add some utility functions for schedule inst commit events.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2555/#review5640 --- Ship it! src/base/remote_gdb.hh

Re: [gem5-dev] Review Request 2554: misc: Rename the GDB "Event" event class to InputEvent.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2554/#review5639 --- Ship it! Ship It! - Ali Saidi On Dec. 5, 2014, 10 a.m., Gabe Black wr

[gem5-dev] Review Request 2556: misc: Generalize GDB single stepping.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2556/ --- Review request for Default. Repository: gem5 Description --- Changeset 10601

Re: [gem5-dev] Review Request 2542: x86: Implement a remote GDB stub.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2542/ --- (Updated Dec. 5, 2014, 10:46 a.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2542: x86: Implement a remote GDB stub.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2542/ --- (Updated Dec. 5, 2014, 10:45 a.m.) Review request for Default. Repository: gem5

[gem5-dev] Review Request 2555: misc: Add some utility functions for schedule inst commit events.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2555/ --- Review request for Default. Repository: gem5 Description --- Changeset 10599

[gem5-dev] Review Request 2554: misc: Rename the GDB "Event" event class to InputEvent.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2554/ --- Review request for Default. Repository: gem5 Description --- Changeset 10598

[gem5-dev] changeset in gem5: sim: Ensure GDB interrupts the simulation at ...

changeset bd68c6838b9f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=bd68c6838b9f description: sim: Ensure GDB interrupts the simulation at an instruction boundary. Use the comInstEventQueue to ensure GDB interrupts the simulation at an instruction b

Re: [gem5-dev] Review Request 2540: sim: Ensure GDB interrupts the simulation at an instruction boundary.

> On Dec. 4, 2014, 6:50 p.m., Steve Reinhardt wrote: > > src/base/remote_gdb.cc, line 2 > > > > > > date? Fixed. > On Dec. 4, 2014, 6:50 p.m., Steve Reinhardt wrote: > > src/base/remote_gdb.cc, line 255 > >

Re: [gem5-dev] Review Request 2540: sim: Ensure GDB interrupts the simulation at an instruction boundary.

> On Dec. 4, 2014, 6:59 p.m., Steve Reinhardt wrote: > > src/base/remote_gdb.hh, line 118 > > > > > > I'd be tempted to rename the other Event class rather than have to > > disambiguate here, but I understand if you don't w

[gem5-dev] changeset in gem5: cpu: Only check for PC events on instruction ...

changeset 1eec33d2fc52 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=1eec33d2fc52 description: cpu: Only check for PC events on instruction boundaries. Only the instruction address is actually checked, so there's no need to check repeatedly while we

[gem5-dev] changeset in gem5: misc: Make the GDB register cache accessible ...

changeset 25ecfc14f73f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=25ecfc14f73f description: misc: Make the GDB register cache accessible in various sized chunks. Not all ISAs have 64 bit sized registers, so it's not always very convenient to acce

Re: [gem5-dev] Review Request 2538: misc: Make the GDB register cache accessible in various sized chunks.

> On Dec. 4, 2014, 4:01 p.m., Steve Reinhardt wrote: > > src/base/remote_gdb.hh, line 157 > > > > > > a comment here like '// size of cache in bytes' would be nice just to > > be clear (and since that has changed) Fixed.

Re: [gem5-dev] Review Request 2546: scons: Avoid implicit command dependencies

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2546/ --- (Updated Dec. 5, 2014, 8:44 a.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2516: config: Add options to take/resume from SimPoint checkpoints

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2516/ --- (Updated Dec. 5, 2014, 8:36 a.m.) Review request for Default. Repository: gem5

[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simpl