scons: *** [build/ALPHA/systemc/utils/vcd.do] Error 1
scons: *** [build/MIPS/systemc/utils/vcd.do] Error 1
scons: *** [build/NULL/systemc/utils/vcd.do] Error 1
scons: *** [build/NULL_MOESI_hammer/systemc/utils/vcd.do] Error 1
scons: *** [build/NULL_MESI_Two_Level/systemc/utils/vcd.do] Error 1
scons
Hello Giacomo Travaglini, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13125
to look at the new patch set (#10).
Change subject: cpu,arch-arm: Initialise data members
Hello Gabe Black, Anthony Gutierrez, Alec Roelke, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13715
to look at the new patch set (#4).
Change subject: arch,cpu: Add vector predicate registers
Hello Gabe Black, Anthony Gutierrez, Alec Roelke, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13715
to look at the new patch set (#5).
Change subject: arch,cpu: Add vector predicate registers
Pau Cabre has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/14417 )
Change subject: cpu: Made LTAGE parameters configurable
..
cpu: Made LTAGE parameters configurable
This inc
Pau Cabre has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/14215 )
Change subject: cpu: Fixed useful counter handling in LTAGE
..
cpu: Fixed useful counter handling in LTAGE
Pau Cabre has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/14216 )
Change subject: cpu: Fixes on the loop predictor part of LTAGE
..
cpu: Fixes on the loop predictor part of L
Giacomo Travaglini has uploaded a new patch set (#15) to the change
originally created by Giacomo Gabrielli. (
https://gem5-review.googlesource.com/c/public/gem5/+/13128 )
Change subject: base, ext: Ported circlebuf to CircularQueue
Hello Gabe Black, Jason Lowe-Power, Sudhanshu Jha, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/14435
to look at the new patch set (#2).
Change subject: cpu: split LTAGE implementation into a base TAGE and a
deriv
Pau Cabre has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/14535
Change subject: cpu: Added new stats to TAGE and LTAGE branch predictors
..
cpu: Added new stats to TAGE and LTAGE br
Ivan Pizarro has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/14555
Change subject: arch-arm: Additional bits in misc ARM registers to use with
the TLB and page walker
..
arch-arm
Hello Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13515
to look at the new patch set (#8).
Change subject: arch-arm,cpu: Add initial support for Arm SVE
...
Hello Gabe Black, Anthony Gutierrez, Alec Roelke, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13715
to look at the new patch set (#6).
Change subject: arch,cpu: Add vector predicate registers
Hello Giacomo Travaglini, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13125
to look at the new patch set (#11).
Change subject: cpu,arch-arm: Initialise data members
Hello Gabe Black, Anthony Gutierrez, Alec Roelke, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13715
to look at the new patch set (#7).
Change subject: arch,cpu: Add vector predicate registers
Ivan Pizarro has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/14575
Change subject: arch-arm: Reverting some changes in the headers for tlb and
table_walker files to ease the review with the previous implementation and
reverting miscregs_types.hh
16 matches
Mail list logo