[gem5-dev] SimObject Param types which are template classes

Hi folks. I'm trying to create a SimObject out of a templated class (the python Param type uses a specialization of it), and the pybind11 generated code doesn't compile because the predeclaration of the class type isn't syntactically correct since it's a template. I can work around this problem by,

[gem5-dev] Change in gem5/gem5[master]: config: Make parameter conversion handle integers in other bases.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/16504 Change subject: config: Make parameter conversion handle integers in other bases. .. config: Make parameter conve

[gem5-dev] Change in gem5/gem5[master]: systemc: Export the tlm::tlm_global_quantum class to python.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/16503 Change subject: systemc: Export the tlm::tlm_global_quantum class to python. .. systemc: Export the tlm::tlm_global_

[gem5-dev] Change in gem5/gem5[master]: systemc: Export the sc_core::sc_time class to python.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/16502 Change subject: systemc: Export the sc_core::sc_time class to python. .. systemc: Export the sc_core::sc_time class

Re: [gem5-dev] [gem5-users] GPU

HI : I built the HSAIL_X86 model for gem5. I also created the an executable "hello" using g++ and openCL runtimes. I was able to build the required .asm file using the AMD High-Level-Compiler ( HLC ) provided in AMD git repo. However when i try to run the program , i get an error : unknown HSA Ob

[gem5-dev] Change in gem5/gem5[master]: base: Fix enums checkpointing

Hello Gabe Black, Jason Lowe-Power, Daniel Carvalho, Andreas Sandberg, Ciro Santilli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16382 to look at the new patch set (#2). Change subject: base: Fix enums checkpointing .

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Move GICv3 detection at startup time

Hello Anouk Van Laer, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16483 to review the following change. Change subject: arch-arm: Move GICv3 detection at startup time ..

[gem5-dev] Change in gem5/gem5[master]: configs: Add DerivO3CPU type option in starter_fs.py

Hello Ciro Santilli, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16482 to review the following change. Change subject: configs: Add DerivO3CPU type option in starter_fs.py .

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix fast build broken due to unused variable

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/16463 ) Change subject: cpu: Fix fast build broken due to unused variable .. cpu: Fix fast build broken due

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix fast build broken due to unused variable

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/16463 Change subject: cpu: Fix fast build broken due to unused variable .. cpu: Fix fast build broken due to unuse

[gem5-dev] Change in gem5/gem5[master]: cpu: Add ISA* getter in Thread interface

Hello Anthony Gutierrez, Jason Lowe-Power, Andreas Sandberg, Giacomo Gabrielli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16462 to look at the new patch set (#2). Change subject: cpu: Add ISA* getter in Thread interface

[gem5-dev] Change in gem5/gem5[master]: arch-arm, cpu: Add initial support for Arm SVE

Giacomo Travaglini has uploaded a new patch set (#13) to the change originally created by Giacomo Gabrielli. ( https://gem5-review.googlesource.com/c/public/gem5/+/13515 ) Change subject: arch-arm,cpu: Add initial support for Arm SVE ...

[gem5-dev] Change in gem5/gem5[master]: cpu: Add ISA* getter in Thread interface

Hello Giacomo Gabrielli, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16462 to review the following change. Change subject: cpu: Add ISA* getter in Thread interface .

[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests