[gem5-dev] Change in gem5/gem5[refs/meta/config]: Review access change

2020-02-11 Thread Bobby R. Bruce (Gerrit)
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/25283 ) Change subject: Review access change .. Review access change Change-Id: I05002faec1f3d36698885bbec4d639f663e2

[gem5-dev] L3 Cache in MOESI_AMD_Base & GPU_VIPER Protocols

2020-02-11 Thread Daniel Gerzhoy
Hello, Question about the L3 cache's role in the MOESI_AMD_Base protocol (and by extension GPU_VIPER which seems to extend it). There seems to be an l3 cache in the directory controller, but it looks like the ports that go to the L3 Cache are never activated (I added some dprintfs in the .sm file

Re: [gem5-dev] SLICC Transition Question

2020-02-11 Thread Daniel Gerzhoy
Thanks Jason! I see the check functions, so that all makes sense now. (The next question is about a specific protocol so I'll make a separate thread) Cheers, Dan On Tue, Feb 11, 2020 at 12:28 PM Jason Lowe-Power wrote: > Hi Dan, > > This is for an advanced feature :). This is used for the res

Re: [gem5-dev] SLICC Transition Question

2020-02-11 Thread Jason Lowe-Power
Hi Dan, This is for an advanced feature :). This is used for the resource stalls feature. Resource stalls are used to model bandwidth to different structures. This is saying that on the transition from I to I_M0 will access the L1D0TagArrayRead and L2TagArrayRead. In the background, this calls che

[gem5-dev] SLICC Transition Question

2020-02-11 Thread Daniel Gerzhoy
Hello, I went through the learning gem5 book to learn slicc (finally) and it made sense to me through that. But I've been looking through the MOESI_AMD_Base-CorePair.sm file (among others) and I've seen a syntax I don't understand. transition(I, C0_Store_L1miss, I_M0) {L1D0TagArrayRead, L2TagArra

Re: [gem5-dev] Ruby Checkpointing Broken

2020-02-11 Thread Giacomo Travaglini
Thanks Timothy, I have created a JIRA ticket for it: https://gem5.atlassian.net/browse/GEM5-331 In the meantime I am considering about adding a ruby-cpt test to long regressions. Giacomo From: gem5-dev on behalf of Timothy Hayes Sent: 06 February 2020 23:02

[gem5-dev] Change in gem5/gem5[master]: arch: Get rid of the generic mmapped IPR mechanism.

2020-02-11 Thread Gabe Black (Gerrit)
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/23186 ) Change subject: arch: Get rid of the generic mmapped IPR mechanism. .. arch: Get rid of the generic mmapped IPR mechanism. J

[gem5-dev] Change in gem5/gem5[master]: mem: Eliminate the now unused GENERIC_IPR request flag.

2020-02-11 Thread Gabe Black (Gerrit)
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/23187 ) Change subject: mem: Eliminate the now unused GENERIC_IPR request flag. .. mem: Eliminate the now unused GENERIC_IPR request

[gem5-dev] Change in gem5/gem5[master]: arm: Call pseudoInst directly from the mmapped IPR handlers.

2020-02-11 Thread Gabe Black (Gerrit)
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/23185 ) Change subject: arm: Call pseudoInst directly from the mmapped IPR handlers. .. arm: Call pseudoInst directly from the mmappe

[gem5-dev] Change in gem5/gem5[master]: tests, misc: update TESTING.md documentation

2020-02-11 Thread Giacomo Travaglini (Gerrit)
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/24526 ) Change subject: tests,misc: update TESTING.md documentation .. tests,misc: update TESTING.md documentation * Documen