Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34166 )
Change subject: mem: Re-remove the arch/isa_traits.hh include in the base
prefetcher.
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mem: Re-remove the arch/isa_trait
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30316 )
Change subject: mem: Add HTM fields to Request
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mem: Add HTM fields to Request
This starts the support of Hardware
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30321 )
Change subject: cpu: Add HTM Instruction Flags
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cpu: Add HTM Instruction Flags
IsHtmStart: Starts a HTM transactio
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30322 )
Change subject: cpu: Add HTM CPU API
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cpu: Add HTM CPU API
JIRA: https://gem5.atlassian.net/browse/GEM5-587
Chang
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30320 )
Change subject: cpu: Add HtmCpu DebugFlag
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cpu: Add HtmCpu DebugFlag
JIRA: https://gem5.atlassian.net/browse/GEM5-
Hi Gabe,
I agree with Isaac, some prefetchers use the page size to avoid crossing
page boundaries. These are prefetchers operate on the PA space and have
no access to the TLB to avoid the extra complexity or because they are
far from the core (e.g., L3 prefetcher).
Some other prefetchers operate
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34177 )
Change subject: base: Minor cleanup of the ChunkGenerator.
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base: Minor cleanup of the ChunkGenerator.
Minor st
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34178 )
Change subject: dev: Stop using the OS page size in the IDE controller.
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dev: Stop using the OS page size in the
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34176 )
Change subject: mem: Use the page size from the TLB in the translating port
proxy.
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mem: Use the page size fr
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34172 )
Change subject: mem,sim: Get the page size from the page table in SE mode.
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mem,sim: Get the page size from the
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34171 )
Change subject: dev,arm: Use the ArmSystem::PageBytes constant in the
generic timer.
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dev,arm: Use the ArmSys
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34175 )
Change subject: arch: Report the page size from the TLB.
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arch: Report the page size from the TLB.
The TLB know
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34174 )
Change subject: gpu: Use X86ISA instead of TheISA in compute_unit.cc.
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gpu: Use X86ISA instead of TheISA in comp
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34173 )
Change subject: gpu: Stop using TheISA in the GPU TLB.
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gpu: Stop using TheISA in the GPU TLB.
This class is de
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34170 )
Change subject: arm: Replicate the PageBytes constant in the ArmSystem
class.
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arm: Replicate the PageBytes c
Hi,
I'm not using Ruby, so just talking about classic.
Before the code included support for the TLBs, the prefetchers used the
page size to detect page-crossing prefetches in order to discard them.
Now it uses that to decide if it can do a direct prefetch or it needs to
check the TLB for a tr
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34118 )
Change subject: base: Cleanup debug flags API
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base: Cleanup debug flags API
The debug flags API has a couple of qui
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34116 )
Change subject: scons: Simplify arch enum generation
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scons: Simplify arch enum generation
C++ allows a trailing com
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34117 )
Change subject: base: Remove unused Debug::All flag
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base: Remove unused Debug::All flag
The Debug::All flag doesn't
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34120 )
Change subject: python: Remove unused debug APIs
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python: Remove unused debug APIs
The following APIs are not export
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34115 )
Change subject: base: Cleanup Debug::CompoundFlag
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base: Cleanup Debug::CompoundFlag
Compound flags are currently co
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34119 )
Change subject: python: Add the ability to check if a debug flag has been
enabled
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python: Add the ability to chec
Actually that's not *quite* the end for isa_traits.hh since the system
class uses the PageBytes and PageShift internally to allocate physical
memory. It's still very close though.
Gabe
On Mon, Sep 7, 2020 at 1:06 AM Gabe Black wrote:
> Hi folks. I've *almost* eliminated use of the getPageBytes
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34168 )
Change subject: null,sim: Add name() to the dummy CPU and remove two #if
THE_ISAs.
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null,sim: Add name() to t
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34167 )
Change subject: sparc,sim: Remove special handling of SPARC in the clone
system call.
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sparc,sim: Remove spec
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34169 )
Change subject: arch: Move many of the generic files outside an NULL guard.
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arch: Move many of the generic file
Hi folks. In gem5, there is a simple but useful utility class called the
ChunkGenerator which takes a region of memory and a size, and breaks the
region into chunks which are broken on that size aligned boundaries.
So for instance, if you wanted to translate every page that some big array
was loca
Hi folks. I've *almost* eliminated use of the getPageBytes and getPageShift
functions in the System class, which in combination with a change from
Andreas will eliminate the need for the isa_traits.hh switching header file.
The only use left is in the Ruby and cache prefetchers:
mem/cache/prefetc
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