Hi everyone,
I noticed that gem5 (I currently use 20.0.0.3) implemented PIPT, but how come
it didn't implement VIPT like MARSSx86?
Thanks!
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_
hi all,I am learning gem5, but in the process of Gdb debugging, I did not
understand how L1cache and l2 cache are reflected in gem5. For example, after
l1 miss, search in l2. do you someome tell me?
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsu
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36115 )
Change subject: arch-arm: move serialize and unserialize definition to cpp
file
..
arch-arm: move serialize
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36116 )
Change subject: arch-arm: serialize miscregs as a map
..
arch-arm: serialize miscregs as a map
This will preve
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36135 )
Change subject: sim: create SERIALIZE_MAP and UNSERIALIZE_MAP
..
sim: create SERIALIZE_MAP and UNSERIALIZE_MAP
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35755 )
Change subject: configs: Remove dangling reference to bus port in devices.py
..
configs: Remove dangling reference to
I found that Gabe black posted some information about smt in maillist-dev.
What I want to ask is, when can I use the smt function in fs mode, I am
looking forward to it.
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-d
Hi Huayi,
Previously, SMT for X86 is currently not supported. However, there is some
progress on supporting SMT+X86 recently:
https://gem5-review.googlesource.com/c/public/gem5/+/35837
Please keep track of the progress here,
- on Jira issue: https://gem5.atlassian.net/browse/GEM5-332
- on Gerrit:
Hi all (and specifically our AMD colleagues),
Does anyone know how real hardware assigns APIC IDs in x86? We need to do
something more than just use the CPU number if we want to support multiple
hardware threads.
We have a proposal here:
https://gem5-review.googlesource.com/c/public/gem5/+/35837.
Kyle Roarty has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/33656 )
Change subject: gpu-compute,mem-ruby: Properly create/handle
WriteCompletePkts
..
gpu-compute,mem-ruby: Properly create/h
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36155 )
Change subject: fastmodel: Fix up for the new standardized create() methods.
..
fastmodel: Fix up for the new stan
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36156 )
Change subject: arch-x86: Make CPUID vendor string a param
..
arch-x86: Make CPUID vendor string a param
Mod
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36157 )
Change subject: scons: Raise an exception when scons is run a Python2
environment
..
scons: Raise an exception
Kyle Roarty has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36159 )
Change subject: configs: python3 compatibility for apu_se
..
configs: python3 compatibility for apu_se
This patc
Kyle Roarty has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36158 )
Change subject: util: Update GCN dockerfile for python3
..
util: Update GCN dockerfile for python3
This patch in
Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36175 )
Change subject: sim,python: Flip logic on loopback listeners
..
sim,python: Flip logic on loopback listeners
16 matches
Mail list logo