Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/58634 )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: misc: Add KCONFIG.md file which talks about Kconfi
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58811 )
Change subject: fastmodel: Export more CortexR52 reset pin
..
fastmodel: Export more CortexR52 reset pin
Change
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58814 )
Change subject: fastmodel: Add CortexA76 artifact reset port
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fastmodel: Add CortexA76 artifact reset port
Th
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58810 )
Change subject: fastmodel: Add a special reset interface to consolidate
reset logic
..
fastmodel: Add a speci
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58812 )
Change subject: fastmodel: Export more CortexA76 reset pin
..
fastmodel: Export more CortexA76 reset pin
Change
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58813 )
Change subject: fastmodel: Add CortexR52 artifact reset port
..
fastmodel: Add CortexR52 artifact reset port
Th
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58809 )
Change subject: scons: Fix script failed when default files not found
..
scons: Fix script failed when default f
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58790 )
Change subject: stdlib, configs: Migrate riscv-ubuntu-run example to
Simulator
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stdlib, configs: Migrate risc
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58789 )
Change subject: stdlib: Add checkpoint to Simulator
..
stdlib: Add checkpoint to Simulator
Change-Id: I58b686b6b4
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58769 )
Change subject: tests: Disable failing MI_Example/Timing CPU X86 Boot Tests
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tests: Disable failing MI_Example/
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58770 )
Change subject: tests: Remove 8-core boot tests for Timing and Atomic
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tests: Remove 8-core boot tests for Timi
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/58473 )
Change subject: arch-vega: Implement SOP2 S_MUL_HI instructions
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arch-vega: Implement SOP2 S_MUL_HI instructions
Two
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57296 )
(
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: Added upstream_nodes to Abstract
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57297 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: AbstractController unaddressed p
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57292 )
Change subject: cpu: Handle external TLBI Sync requests in O3CPU
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cpu: Handle external TLBI Sync requests in O3CPU
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57293 )
Change subject: mem-ruby: Support for unaddressed mem requests in the
RubyRequest
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mem-ruby: Support for unaddre
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57295 )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: Add TLBI callbacks to the RubyPo
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