changeset 953d7b741619 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=953d7b741619
description:
cpu: Fix memoryIssueLimit checking in Minor
This patch fixes the checking of the number of memory instructions
issued
per cycles in the Minor CPU.
changeset 5d7af9fa9809 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5d7af9fa9809
description:
config: SystemC Gem5Control top level additions
This patch cleans up a few style issues and adds a few capabilities to
the
SystemC top level
changeset 7c4f1d0a8cff in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7c4f1d0a8cff
description:
cpu: Fix retries on barrier/store in Minor's store buffer
This patch fixes a case where a store in Minor's store buffer never
leaves the store buffer as
changeset 997be6ba467e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=997be6ba467e
description:
config: Fix to SystemC example's event handling
This patch fixes checkpoint restore in the SystemC hosting example by
handling
early PollEvent events
changeset e622a3e2ed14 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e622a3e2ed14
description:
arm: Fix TLB ignoring faults when table walking
This patch fixes a case where the Minor CPU can deadlock due to the lack
of a response to TLB request
On Nov. 19, 2014, 12:22 a.m., Cagdas Dirik wrote:
Please ignore my last review. I made a mistake with my patches.
In FS, X86 mode I was able to boot with python variant, checkpoint, run a
short program. Then I was able to restore from checkpoint and run the same
program again. And
On Nov. 19, 2014, 12:22 a.m., Cagdas Dirik wrote:
Please ignore my last review. I made a mistake with my patches.
In FS, X86 mode I was able to boot with python variant, checkpoint, run a
short program. Then I was able to restore from checkpoint and run the same
program again. And
The convention is even documented (by gem5's documentation standards that must
almost make it a law):
http://gem5.org/SimObjects
point 9:
Later, the first time that the user script calls simulate(), call startup() on
each SimObject. This is the point where SimObjects that do self-initiated
On Nov. 19, 2014, 12:22 a.m., Cagdas Dirik wrote:
Please ignore my last review. I made a mistake with my patches.
In FS, X86 mode I was able to boot with python variant, checkpoint, run a
short program. Then I was able to restore from checkpoint and run the same
program again. And
On Nov. 19, 2014, 12:22 a.m., Cagdas Dirik wrote:
Please ignore my last review. I made a mistake with my patches.
In FS, X86 mode I was able to boot with python variant, checkpoint, run a
short program. Then I was able to restore from checkpoint and run the same
program again. And
The member functions before_end_of_elaboration and end_of_elaboration are
defined on sc_core::sc_module and the SystemC simulation kernel handles calling
them at the appropriate times.
Try printing something in main.cc:SimControl::before_end_of_elaboration and you
should see that print
changeset 1a9e235cab09 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1a9e235cab09
description:
config: Fix checkpoint restore in C++ config example
This patch fixes the checkpoint restore option in the example of C++
configuration (util/cxx_config).
It's better to see the cxx_config and systemc examples as just that, examples.
The -s/-r check in SystemC is just forgotten. I really expected only one
feature to be tried at a time, so -s/-r together with -c is not well explained.
I expect any practical use of either feature to involve
OK, Cagdas. I've pushed the fix I had in mind to our local repo. You should
see it with the next set of patches that Ali or Andreas push.
- Andrew
-Original Message-
From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Andrew Bardsley
via gem5-dev
Sent: 08 November 2014 17
The PollEvent seems to be the GDB connect mechanism. I don't know if that's
changed or I didn't sufficiently test the checkpoint restore. Oh well.
llEvent seems to be the GDB connect mechanism. I don't know if that's changed
to insert an earlier event (I have a vague memory of some GDB fix
Cagdas, can you try adding the line:
config_manager-startup()
at line 268 in util/cxx_config/main.cc (after the loadState(checkpoint) line).
I've tried your ARM example (superficially, on my home machine) and it seems to
fix the problem there with running 'hello' with your setup instructions.
changeset 58d5d471b598 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=58d5d471b598
description:
cpu: Fix barrier push to store buffer when full bug in Minor
This patch fixes a bug where a completing load or store which is also a
barrier can push a
changeset 5744891a444b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5744891a444b
description:
base: Reimplement the DPRINTF mechanism in a Logger class
This patch adds a Logger class encapsulating dprintf. This allows
variants of DPRINTF logging
changeset 16fd06ecdb64 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=16fd06ecdb64
description:
sim: SystemC hosting
This patch hosts gem5 onto SystemC scheduler. There's already an
upstream
review board patch that does something similar but this
On Sept. 29, 2014, 1:19 p.m., Nathan Binkert wrote:
src/base/trace.cc, line 5
http://reviews.gem5.org/r/2456/diff/1/?file=42022#file42022line5
This isn't necessary for stuff in base, right?
Andrew Bardsley wrote:
Is there a copyright policy thing I don't know about base?
On Sept. 29, 2014, 1:08 p.m., Nathan Binkert wrote:
src/SConscript, line 66
http://reviews.gem5.org/r/2425/diff/1/?file=41733#file41733line66
Why not just have one flag called skip_no_python?
Andrew Bardsley wrote:
I left the swig related and embedded python-related flags
On Sept. 29, 2014, 1:19 p.m., Nathan Binkert wrote:
src/base/trace.cc, line 5
http://reviews.gem5.org/r/2456/diff/1/?file=42022#file42022line5
This isn't necessary for stuff in base, right?
Is there a copyright policy thing I don't know about base?
On Sept. 29, 2014, 1:19 p.m.,
On Sept. 29, 2014, 1:08 p.m., Nathan Binkert wrote:
src/SConscript, line 66
http://reviews.gem5.org/r/2425/diff/1/?file=41733#file41733line66
Why not just have one flag called skip_no_python?
I left the swig related and embedded python-related flags separate as I thought
it was
changeset ec1af95a2958 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ec1af95a2958
description:
config: Cleanup .json config file generation
This patch 'completes' .json config files generation by adding in the
SimObject references and String-valued
changeset 3f943443ae30 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3f943443ae30
description:
base: Add getSectionNames to IniFile
Add an accessor to IniFile to list all the sections in the file.
diffstat:
src/base/inifile.cc | 10 ++
changeset a7cb233caa7b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a7cb233caa7b
description:
cpu: Fix memory access in Minor not setting parent Request flags
This patch fixes cases where uncacheable/memory type flags are not set
correctly on a
changeset bf52480abd01 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bf52480abd01
description:
style: Fix line continuation, especially in debug messages
This patch closes a number of space gaps in debug messages caused by
the incorrect use of line
changeset 82a4fa2d19a0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=82a4fa2d19a0
description:
sim: Fix checkpoint restore for Ticked
This patch makes restoring the 'lastStopped' value for Ticked-containing
objects (including MinorCPU) optional so
changeset 85001c018d4c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=85001c018d4c
description:
arm: ISA X31 destination register fix
This patch substituted the zero register for X31 used as a
destination register. This prevents false dependencies
changeset 384d554cea8c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=384d554cea8c
description:
cpu: Minor CPU add regression tests for ARM and ALPHA
This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
changeset ebb376f73dd2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ebb376f73dd2
description:
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines,
.
Your proposal sounds great to me. Thanks a lot for being flexible.
Steve
On Tue, Jul 1, 2014 at 10:33 AM, Andrew Bardsley via gem5-dev
gem5-dev@gem5.org wrote:
Only slight modification to your proposal:
How about I get rid of Ticked and flatten evaluate/minorTrace into the
classes which need
Only slight modification to your proposal:
How about I get rid of Ticked and flatten evaluate/minorTrace into the classes
which need it.
I think that there aren't actually any cases where there need to be virtual
calls to any of
its member functions.
I assume that by ClockedModule you mean
On June 4, 2014, 8:15 p.m., Steve Reinhardt wrote:
src/cpu/minor/Expr.py, line 48
http://reviews.gem5.org/r/2279/diff/1/?file=39827#file39827line48
This is pretty interesting... it would be nice to generalize this
capability and not make it Minor-specific
Andrew Bardsley
On June 4, 2014, 8:15 p.m., Steve Reinhardt wrote:
Nice! I didn't have time to read all the code closely, but I did notice a
few things, and wanted to give feedback before I forgot.
Basically the comments boil down to three things:
1. There are several pieces (Named,
changeset 1ab8753de4d8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1ab8753de4d8
description:
cpu: Timebuf const accessors
Add const accessors for timebuf elements.
diffstat:
src/cpu/timebuf.hh | 32 +---
1 files changed, 21
changeset 0f00b9e7305a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0f00b9e7305a
description:
cpu: Useful getters for ActivityRecorder
Add some useful getters to ActivityRecorder
diffstat:
src/cpu/activity.hh | 11 +--
1 files changed, 9
changeset 590ba8823163 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=590ba8823163
description:
cpu: Allow setWhen on trace objects
Allow setting of 'when' in trace records. This allows later times
than the arbitrary record creation point to be used
changeset 6cf40d777682 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6cf40d777682
description:
arm: Add branch flags onto macroops
Mark branch flags onto macroops to allow branch prediction before
microop decomposition
diffstat:
changeset 30a20d2072c1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=30a20d2072c1
description:
cpu: Add flag name printing to StaticInst
This patch adds a the member function StaticInst::printFlags to allow
all
of an instruction's flags to be
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