> -Original Message-
> From: Gabe Black
> Sent: 04 March 2021 04:04
> To: Giacomo Travaglini
> Cc: gem5 Developer List
> Subject: Re: [gem5-dev] vector register indexing modes and renaming?
>
>
>
> On Mon, Mar 1, 2021 at 6:48 AM Giacomo Travaglini
>
On Mon, Mar 1, 2021 at 6:48 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:
>
> > -Original Message-
> > From: Gabe Black
> > Sent: 27 February 2021 05:47
> > To: Giacomo Travaglini
> > Cc: gem5 Developer List
> > Subject:
> -Original Message-
> From: Gabe Black
> Sent: 27 February 2021 05:47
> To: Giacomo Travaglini
> Cc: gem5 Developer List
> Subject: Re: [gem5-dev] vector register indexing modes and renaming?
>
> Another question/clarification:
>
> Does any data actua
Another question/clarification:
Does any data actually get shared between the two rename modes? I think you
said there is not, but now I can't find that. Would it work just as well to
have two register files which operate entirely independently? From what I
can tell the "V" registers of Neon in
>
> I will ask within Arm if there's something we can provide to you.
>> In the meantime I gave a quick look at NEON enabled libraries [1]; the
>> Ne10 library provides a set of functions optimized for NEON and a set
>> of examples making use of it [2] (e.g FIR filter, GEMM etc etc).
>>
>> You
On Wed, Feb 24, 2021 at 8:05 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:
>
>
> > -Original Message-
> > From: Gabe Black
> > Sent: 24 February 2021 15:24
> > To: Giacomo Travaglini
> > Cc: gem5 Developer List
> > Subjec
> -Original Message-
> From: Gabe Black
> Sent: 24 February 2021 15:24
> To: Giacomo Travaglini
> Cc: gem5 Developer List
> Subject: Re: [gem5-dev] vector register indexing modes and renaming?
>
> So, I started really diving into the interfaces in ThreadCo
So, I started really diving into the interfaces in ThreadContext and
ExecContext and their various implementations. What I wanted to do was to
define a much narrower set of maybe 3 virtual functions that actually
implements the core of what's needed, and not 15-20 different independent
virtual
That said, the first would avoid adding another register file while that
would still mean plumbing new interfaces all over the place for all the
ThreadContext and ExecContexts, etc. Once all that code is generic and you
can add or remove register files willy-nilly, it might make sense to switch
to
>
>
> > Hey ARM folks. Could someone please explain to me what the deal is with
> the
> > vector registers and renaming modes? What is fundamentally going on
> there?
> > My best guess is that the granularity that the registers are being
> renamed at
> > changes between the modes, or in other
Hi Gabe
> -Original Message-
> From: Gabe Black via gem5-dev
> Sent: 23 February 2021 08:54
> To: gem5 Developer List
> Cc: Gabe Black
> Subject: [gem5-dev] vector register indexing modes and renaming?
>
> Hey ARM folks. Could someone please explain to me what the deal is with the
>
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