>
> Also, I think with this flag in place we ought to be able to get rid
> of the tlb_mode setting; the TLB can just look and see whether
> isInstFetch() is true to decide how to handle the request... does
> anyone agree or disagree?
>
Without thinking too deeply this part seems ok to me. It m
Korey: I was going to fix this in inorder too, but there are two
places where Request objects are allocated (tlb_unit.hh and
cache_unit.cc) and I wasn't sure why there were two, if both needed to
be fixed, or what.
Also, I think with this flag in place we ought to be able to get rid
of the tlb_mod
changeset 7ed8937e375a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7ed8937e375a
description:
Fix setting of INST_FETCH flag for O3 CPU.
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily w
changeset 50125d42559c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=50125d42559c
description:
Rename internal Request fields to start with '_'.
The inconsistency was causing a subtle bug with some of the
constructors where the params had the same name a
changeset 9e35cdc95e81 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9e35cdc95e81
description:
Clean up some inconsistencies with Request flags.
diffstat:
4 files changed, 11 insertions(+), 20 deletions(-)
src/arch/arm/tlb.cc |2 +-
src/arch/sparc/tlb.cc |2 +
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed.
* build/ALPHA_SE/tests/fast/quick/00.hel
