[m5-dev] Alpha data faults taking fields from the MachInst

Hi Alpha experts. I'm working towards getting x86 to run in O3, and I'm running into a minor hangup having to do with MachInsts and ExtMachInsts that I won't bother to go into. I could nullify the problem and also simplify some code if I can eliminate this line in Alpha's fault code http://rep

Re: [m5-dev] Review Request: ARM: make predicated-false instruction to move data from a old register.

Ali Saidi wrote: > On Thu, 19 Aug 2010 15:21:24 -0400, Gabriel Michael Black > wrote: > >> Quoting Ali Saidi : >> >> >>> On Tue, 17 Aug 2010 14:19:49 -0400, Gabriel Michael Black >>> wrote: >>> Quoting Steve Reinhardt : > On Sun, Aug 15, 2010 at 6:07 PM,

Re: [m5-dev] Review Request: ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.

O3 only -seems- to execute multiple memory instructions at a time. Each initiateAcc is called one at a time and completes execution before the next starts, so the same thing should apply as far as that goes. Gabe Ali Saidi wrote: > Remember that the timing cpu is only executing one instruction at

Re: [m5-dev] TimingSimpleCPU, x86: sendSplitData + TLB miss

For that we might want two walkers. They'd need to start with different CR3s (roots), interleave, etc. and doing it all in one might be overly complicated. I honestly haven't thought about it deeply. That's with AMD's SVM too, mind you, since I think Intel's VT uses a substantially differen

Re: [m5-dev] TimingSimpleCPU, x86: sendSplitData packet sender states

Quoting Steve Reinhardt : I don't think I changed anything here... hg annotate seems to back me up on that, too. I think the fundamental (but subtle) issue here is that once you successfully send a packet, the ownership for that packet object is conceptually handed off to the recipient, so tech

Re: [m5-dev] TimingSimpleCPU, x86: sendSplitData packet sender states

> -Original Message- > From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On > Behalf Of Steve Reinhardt > Sent: Thursday, August 19, 2010 3:03 PM > To: M5 Developer List > Subject: Re: [m5-dev] TimingSimpleCPU, x86: sendSplitData packet sender > states > > (That said, look

Re: [m5-dev] TimingSimpleCPU, x86: sendSplitData + TLB miss

Note that if/when we get around to supporting virtualization, we'll need to handle nested page table walks too, so if there's a solution to this problem that looks like it would lend itself better to nesting walks too then that would be a preferable direction to go. Steve On Wed, Aug 18, 2010 at

Re: [m5-dev] TimingSimpleCPU, x86: sendSplitData packet sender states

I don't think I changed anything here... hg annotate seems to back me up on that, too. I think the fundamental (but subtle) issue here is that once you successfully send a packet, the ownership for that packet object is conceptually handed off to the recipient, so technically the sender shouldn't

Re: [m5-dev] Review Request: ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.

Remember that the timing cpu is only executing one instruction at a time. If the instruction calls read() and no access isn't set the timing cpu packages up the request ships it out and sets it's state to DcacheWaitResponse. If the instruction doesn't call read() it continues on like nothing happe

Re: [m5-dev] Review Request: ARM: make predicated-false instruction to move data from a old register.

On Thu, 19 Aug 2010 15:21:24 -0400, Gabriel Michael Black wrote: > Quoting Ali Saidi : > >> >> On Tue, 17 Aug 2010 14:19:49 -0400, Gabriel Michael Black >> wrote: >>> Quoting Steve Reinhardt : >>> On Sun, Aug 15, 2010 at 6:07 PM, Min Kyu Jeong >> wrote: > > > I needed to spit

Re: [m5-dev] Review Request: ARM: make predicated-false instruction to move data from a old register.

Quoting Ali Saidi : On Tue, 17 Aug 2010 14:19:49 -0400, Gabriel Michael Black wrote: Quoting Steve Reinhardt : On Sun, Aug 15, 2010 at 6:07 PM, Min Kyu Jeong wrote: I needed to spit out a code that reads from a register, and writes to it again. The thing is arch reg indices are renam

Re: [m5-dev] Review Request: ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.

I don't think that's true, but I may be confused. I think, at least for the timing CPU, that it checks if a read/write was called and doesn't just fall through. The timing CPU would wait forever for a read/write response that would never come otherwise. (digs around a little) I think it's s

Re: [m5-dev] Review Request: Loader: Make the load address mask be a parameter of the system rather than a constant. This allows one two different OS requirements for the same ISA to be handled.

> On 2010-08-19 08:55:19, Nathan Binkert wrote: > > Seems reasonable. How does the mask work and why is it different for two > > different OSes? Can you add a better comment somewhere? > > Ali Saidi wrote: > ARM linux is compiled at some virtual address that is platform dependent > (alth

Re: [m5-dev] Review Request: ARM: make predicated-false instruction to move data from a old register.

On Tue, 17 Aug 2010 14:19:49 -0400, Gabriel Michael Black wrote: > Quoting Steve Reinhardt : > >> On Sun, Aug 15, 2010 at 6:07 PM, Min Kyu Jeong wrote: >>> >>> >>> I needed to spit out a code that reads from a register, and writes to it >>> again. The thing is arch reg indices are renamed (reg

Re: [m5-dev] Review Request: Loader: Make the load address mask be a parameter of the system rather than a constant. This allows one two different OS requirements for the same ISA to be handled.

> On 2010-08-19 08:55:19, Nathan Binkert wrote: > > Seems reasonable. How does the mask work and why is it different for two > > different OSes? Can you add a better comment somewhere? > > Ali Saidi wrote: > ARM linux is compiled at some virtual address that is platform dependent > (alth

Re: [m5-dev] Review Request: ARM: Fix Uncachable TLB requests and decoding of xn bit

> On 2010-08-19 10:12:11, Ali Saidi wrote: > > src/arch/arm/table_walker.hh, line 109 > > > > > > The bit is described by the function name that grabs it. I don't see > > much benefit to having an enum of bit descriptions and

Re: [m5-dev] Review Request: ARM: Add some registers for big loads/stores to support neon.

> On 2010-08-19 09:49:51, Nathan Binkert wrote: > > Shouldn't this be folded into some other diff? > > Ali Saidi wrote: > I'll fold it in to another change that needs it. I don't know that that's the right thing to do. This doesn't fit backward in time because we can't go that far back, an

Re: [m5-dev] Review Request: BUILD: GCC 4.4.1/2 have a bug in their auto-vectorizer that we trip on

> On 2010-08-19 10:53:07, Nathan Binkert wrote: > > SConstruct, line 367 > > > > > > Sorry I didn't read the comment more closely. What exactly is > > happening with CCVERSION? You're saying that if we do something like >

Re: [m5-dev] Review Request: O3: Skipping mem-order violation check for uncachable loads.

> On 2010-08-19 10:33:02, Ali Saidi wrote: > > src/cpu/o3/fetch_impl.hh, line 1153 > > > > > > Fair enough, but it's how all the serial numbers are printed in the > > file. if we want to change it we should probably have a d

Re: [m5-dev] Review Request: BUILD: GCC 4.4.1/2 have a bug in their auto-vectorizer that we trip on

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/202/#review278 --- SConstruct Sorry I didn

Re: [m5-dev] Review Request: ARM: Fix Uncachable TLB requests and decoding of xn bit

> On 2010-08-19 10:12:11, Ali Saidi wrote: > > src/arch/arm/table_walker.hh, line 109 > > > > > > The bit is described by the function name that grabs it. I don't see > > much benefit to having an enum of bit descriptions and

Re: [m5-dev] Review Request: STATS: Fix off-by-one error in distributions.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/203/#review275 --- Ship it! please change STATS: to stats: in the commit message. src/base

Re: [m5-dev] Review Request: ARM: Add I/O devices for booting linux

> On 2010-08-17 14:56:45, Ali Saidi wrote: > > src/base/intmath.hh, line 84 > > > > > > How about a warning if it's called with an exponent > 20? > > > > Steve Reinhardt wrote: > I'd prefer something a little more robust.

Re: [m5-dev] Review Request: ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.

It's not the same issue here. The simple cpus just have their execute/completeAccess methods guarded by a predicate condition test. If nothing happens in there, so be it and the cpu goes onto the next instruction without complaint. The out of order cpu on the other hand needs to know if the instr

Re: [m5-dev] Review Request: ARM: Make sure that software prefetch instructions can't change the state of the TLB

> On 2010-08-19 10:34:00, Nathan Binkert wrote: > > src/arch/arm/faults.hh, line 91 > > > > > > Space after // in comments. I know it's not explicitly stated in the > > style guide, but the examples are consistent and it is w

Re: [m5-dev] Review Request: ARM: Make sure that software prefetch instructions can't change the state of the TLB

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/192/#review271 --- src/arch/arm/faults.hh

Re: [m5-dev] Review Request: O3: Skipping mem-order violation check for uncachable loads.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/200/#review270 --- src/cpu/o3/fetch_impl.hh

Re: [m5-dev] Review Request: ARM: Add system for ARM/Linux and bootstrapping

> On 2010-08-17 15:11:44, Ali Saidi wrote: > > src/arch/arm/linux/atag.hh, line 92 > > > > > > The style guide is silent on the matter > > Nathan Binkert wrote: > It is true that the style guide is silent, but I'd have to

Re: [m5-dev] Review Request: ARM: adding non-speculative/serialize flags for instructions change CPSR

> On 2010-08-19 10:03:17, Nathan Binkert wrote: > > Should this be folded into #179? done. - Ali --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/196/#review255 -

Re: [m5-dev] Review Request: ARM: Add system for ARM/Linux and bootstrapping

> On 2010-08-17 15:11:44, Ali Saidi wrote: > > src/arch/arm/linux/atag.hh, line 92 > > > > > > The style guide is silent on the matter It is true that the style guide is silent, but I'd have to agree with Gabe. Either all on

Re: [m5-dev] Review Request: BASE: Fix genrand to generate both 0s and 1s when max equals one.

> On 2010-08-13 15:57:40, Steve Reinhardt wrote: > > Is this right? Seems like genrand(1) and genrand(2) will now do the same > > thing. Should we be calling ceilLog2(max+1) instead? > > > > Ali Saidi wrote: > You're right Steve, it still fails on powers of two. I tested from 0 to > 10 a

Re: [m5-dev] Review Request: BUILD: GCC 4.4.1/2 have a bug in their auto-vectorizer that we trip on

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/202/#review265 --- SConstruct Nope... see

Re: [m5-dev] Review Request: ARM: DPRINTFs prints disassembly for uops

> On 2010-08-19 10:04:25, Nathan Binkert wrote: > > This isn't really a DPRINTF, is it? Seems like the commit message is wrong. fixed. - Ali --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/199

Re: [m5-dev] Review Request: Loader: Make the load address mask be a parameter of the system rather than a constant. This allows one two different OS requirements for the same ISA to be handled.

> On 2010-08-19 08:55:19, Nathan Binkert wrote: > > Seems reasonable. How does the mask work and why is it different for two > > different OSes? Can you add a better comment somewhere? > > Ali Saidi wrote: > ARM linux is compiled at some virtual address that is platform dependent > (alth

Re: [m5-dev] Review Request: BASE: Fix genrand to generate both 0s and 1s when max equals one.

> On 2010-08-13 15:57:40, Steve Reinhardt wrote: > > Is this right? Seems like genrand(1) and genrand(2) will now do the same > > thing. Should we be calling ceilLog2(max+1) instead? > > > > Ali Saidi wrote: > You're right Steve, it still fails on powers of two. I tested from 0 to > 10 a

Re: [m5-dev] Review Request: MEM: Make CLREX a first class request operation and clear locks in caches when it in received

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/193/#review261 --- src/arch/arm/tlb.hh You

Re: [m5-dev] Review Request: ARM: Fix Uncachable TLB requests and decoding of xn bit

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/189/#review260 --- src/arch/arm/table_walker.hh

Re: [m5-dev] Review Request: O3: Skipping mem-order violation check for uncachable loads.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/200/#review259 --- src/cpu/o3/fetch_impl.hh

Re: [m5-dev] Review Request: BUILD: GCC 4.4.1/2 have a bug in their auto-vectorizer that we trip on

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/202/#review257 --- I hate stuff like this, but such is life. SConstruct

Re: [m5-dev] Review Request: ARM: BX only conditional within at IT block

> On 2010-08-19 09:53:33, Nathan Binkert wrote: > > Shouldn't this be folded into review #182? done. - Ali --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/183/#review243 ---

Re: [m5-dev] Review Request: ARM: DPRINTFs prints disassembly for uops

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/199/#review256 --- This isn't really a DPRINTF, is it? Seems like the commit message is wron

Re: [m5-dev] Review Request: ARM: adding non-speculative/serialize flags for instructions change CPSR

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/196/#review255 --- Should this be folded into #179? - Nathan On 2010-08-13 10:17:02, Ali S

Re: [m5-dev] Review Request: ARM: Add configuration for Linux/Full System

> On 2010-08-19 09:43:43, Nathan Binkert wrote: > > And the ARM license infection begins. By the way, what's with the ALL CAPS > > before the : in the short descriptions? I can understand ARM, but BUILD? i thought that was the thing to do... but I can change it. - Ali

Re: [m5-dev] Review Request: ARM: Change how the AMBA device ID checking is done to make it more generic

> On 2010-08-19 09:47:09, Nathan Binkert wrote: > > Looks fine. Why do all of the files show up as new in reviewboard? Are > > you using the -o option to hg postreview? no idea, yes. - Ali --- This is an automatically generated e-mai

Re: [m5-dev] Review Request: Loader: Make the load address mask be a parameter of the system rather than a constant. This allows one two different OS requirements for the same ISA to be handled.

> On 2010-08-19 08:55:19, Nathan Binkert wrote: > > Seems reasonable. How does the mask work and why is it different for two > > different OSes? Can you add a better comment somewhere? > > Ali Saidi wrote: > ARM linux is compiled at some virtual address that is platform dependent > (alth

Re: [m5-dev] Review Request: ARM: Implement DSB, DMB, ISB

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/186/#review251 --- src/arch/arm/isa/formats/uncond.isa

Re: [m5-dev] Review Request: ARM: Fix Uncachable TLB requests and decoding of xn bit

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/189/#review250 --- src/arch/arm/table_walker.hh

Re: [m5-dev] Review Request: ARM: Implement CLREX

> On 2010-08-19 09:55:36, Nathan Binkert wrote: > > src/arch/arm/isa/insts/misc.isa, line 711 > > > > > > What's this? Seems like random whitespace that should be deleted. gone. > On 2010-08-19 09:55:36, Nathan Binkert wro

Re: [m5-dev] Review Request: ARM: For non-cachable accesses set the UNCACHABLE flag

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/187/#review248 --- Ship it! I'll assume that you're right. - Nathan On 2010-08-13 10:14:2

Re: [m5-dev] Review Request: ARM: Implement DSB, DMB, ISB

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/186/#review246 --- src/arch/arm/isa/formats/branch.isa

Re: [m5-dev] Review Request: ARM: Exclusive accessse must be double word aligned

> On 2010-08-19 09:50:33, Nathan Binkert wrote: > > Commit message has seplling error fixed - Ali --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/173/#review239

Re: [m5-dev] Review Request: ARM: Add some registers for big loads/stores to support neon.

> On 2010-08-19 09:49:51, Nathan Binkert wrote: > > Shouldn't this be folded into some other diff? I'll fold it in to another change that needs it. - Ali --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5s

Re: [m5-dev] Review Request: ARM: Implement CLREX

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/184/#review244 --- src/arch/arm/isa/insts/misc.isa

Re: [m5-dev] Review Request: ARM: BX only conditional within at IT block

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/183/#review243 --- Shouldn't this be folded into review #182? - Nathan On 2010-08-13 10:13

Re: [m5-dev] Review Request: ARM: mark msr/mrs instructions as SerializeBefore/After

> On 2010-08-19 09:51:56, Nathan Binkert wrote: > > src/cpu/o3/iew_impl.hh, line 1195 > > > > > > @todo is probably better since we could in theory use doxygen to help > > us out with these. Done. - Ali

Re: [m5-dev] Review Request: CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflag

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/181/#review241 --- Ship it! - Nathan On 2010-08-13 10:13:08, Ali Saidi wrote: > > ---

Re: [m5-dev] Review Request: ARM: mark msr/mrs instructions as SerializeBefore/After

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/179/#review240 --- src/cpu/o3/iew_impl.hh

Re: [m5-dev] Review Request: ARM: Exclusive accessse must be double word aligned

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/173/#review239 --- Ship it! Commit message has seplling error - Nathan On 2010-08-13 10:0

Re: [m5-dev] Review Request: ARM: Add some registers for big loads/stores to support neon.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/172/#review238 --- Shouldn't this be folded into some other diff? - Nathan On 2010-08-13 1

Re: [m5-dev] Review Request: ARM: Clean up the ISA desc portion of the ARM memory instructions.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/170/#review237 --- Ship it! Since you basically moved a bunch of code around, it would requi

Re: [m5-dev] Review Request: ARM: Change how the AMBA device ID checking is done to make it more generic

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/167/#review236 --- Ship it! Looks fine. Why do all of the files show up as new in reviewboa

Re: [m5-dev] Review Request: ARM: Add configuration for Linux/Full System

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/166/#review235 --- Ship it! And the ARM license infection begins. By the way, what's with t

Re: [m5-dev] Review Request: ARM: Use a stl queue for the table walker state

> On 2010-08-19 08:51:48, Nathan Binkert wrote: > > Why exactly did you make this change. The FifoBuffer class limits (I > > think) the number of entries allowed and you removed that restriction. Are > > you sure you want to do that? we don't really want to limit the number of requests the c

Re: [m5-dev] Review Request: Loader: Make the load address mask be a parameter of the system rather than a constant. This allows one two different OS requirements for the same ISA to be handled.

> On 2010-08-19 08:55:19, Nathan Binkert wrote: > > Seems reasonable. How does the mask work and why is it different for two > > different OSes? Can you add a better comment somewhere? ARM linux is compiled at some virtual address that is platform dependent (although they're almost all the s

Re: [m5-dev] Review Request: Loader: Use address mask provided to load*Symbols when loading the symbols from the symbol table.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/161/#review232 --- Ship it! - Nathan On 2010-08-13 09:42:27, Ali Saidi wrote: > > ---

Re: [m5-dev] Review Request: ARM: Fix an un-initialized variable bug

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/162/#review231 --- Ship it! - Nathan On 2010-08-13 09:42:49, Ali Saidi wrote: > > ---

Re: [m5-dev] Review Request: Loader: Make the load address mask be a parameter of the system rather than a constant. This allows one two different OS requirements for the same ISA to be handled.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/160/#review230 --- Seems reasonable. How does the mask work and why is it different for two

Re: [m5-dev] Review Request: ARM: Use a stl queue for the table walker state

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/158/#review229 --- Why exactly did you make this change. The FifoBuffer class limits (I thin

[m5-dev] Cron /z/m5/regression/do-regression quick

* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby FAILED! * build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * b