Re: [m5-dev] Alpha data faults taking fields from the MachInst

I guess it was too good to be true. When I actually -used- StaticInstPtr by itself, gcc didn't like passing an incomplete type by value. Gabe Black wrote: > In the process of implementing this, I wound up creating an include loop > between static_inst.hh and sim/faults.hh. All I really needed was

Re: [m5-dev] Alpha data faults taking fields from the MachInst

In the process of implementing this, I wound up creating an include loop between static_inst.hh and sim/faults.hh. All I really needed was StaticInstPtr, so it seemed silly that this didn't work. I remember having a similar problem with PacketPtr, I think. Anyway, I have a patch where I separate ou

[m5-dev] changeset in m5: Faults: Get rid of some commented out code in s...

changeset ffea4f79784f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=ffea4f79784f description: Faults: Get rid of some commented out code in sim/faults.hh. diffstat: src/sim/faults.hh | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diffs (12 lines): diff

[m5-dev] changeset in m5: Power: Get rid of unused checkFpEnableFault.

changeset d9b98534a872 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=d9b98534a872 description: Power: Get rid of unused checkFpEnableFault. This function was brought in from another ISA and doesn't actually do anything or get used. diffstat: src/arc

[m5-dev] changeset in m5: X86: Create a directory for files that define r...

changeset 0f0c231e3e97 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=0f0c231e3e97 description: X86: Create a directory for files that define register indexes. This is to help tidy up arch/x86. These files should not be used external to the ISA. diffst

[m5-dev] changeset in m5: ISA: Get rid of old, unused utility functions c...

changeset 3b0c4b819651 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3b0c4b819651 description: ISA: Get rid of old, unused utility functions cluttering up the ISAs. diffstat: src/arch/alpha/ev5.cc | 47 - src/arch/alpha/utility.

[m5-dev] changeset in m5: X86: Get rid of the flagless microop constructor.

changeset bdd926760470 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=bdd926760470 description: X86: Get rid of the flagless microop constructor. This will reduce clutter in the source and hopefully speed up compilation. diffstat: src/arch/x86/isa/formats/st

[m5-dev] changeset in m5: X86: Make the TLB fault instead of panic when s...

changeset b1e69203bae9 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=b1e69203bae9 description: X86: Make the TLB fault instead of panic when something is unmapped in SE mode. The fault object, if invoked, would then panic. This is a bit less direct, but

[m5-dev] changeset in m5: X86: Make the x86 ExtMachInst serializable with...

changeset 3f32191bcf66 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3f32191bcf66 description: X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR. diffstat: src/arch/x86/SConscript |1 + src/arch/x86/types.cc | 107 +++

[m5-dev] changeset in m5: X86: Mark serializing macroops and regular inst...

changeset b49144029ec8 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=b49144029ec8 description: X86: Mark serializing macroops and regular instructions as such. diffstat: src/arch/x86/isa/formats/cpuid.isa | 2 + s

[m5-dev] changeset in m5: X86: Define a noop ExtMachInst.

changeset 072f8b921599 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=072f8b921599 description: X86: Define a noop ExtMachInst. diffstat: src/arch/x86/isa_traits.hh | 12 1 files changed, 12 insertions(+), 0 deletions(-) diffs (22 lines): diff -r b4914

[m5-dev] changeset in m5: X86: Consolidate extra microop flags into one p...

changeset 3d8a23caa1ef in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3d8a23caa1ef description: X86: Consolidate extra microop flags into one parameter. This single parameter replaces the collection of bools that set up various flavors of microops. A fl

[m5-dev] changeset in m5: X86: Add a .serializing directive that makes a ...

changeset 3a6468fa514f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3a6468fa514f description: X86: Add a .serializing directive that makes a macroop serializing. This directive really just tells the macroop to set IsSerializing and IsSerializeAfter on

[m5-dev] changeset in m5: CPU: Make the constants for StaticInst flags vi...

changeset 0a32de653c10 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=0a32de653c10 description: CPU: Make the constants for StaticInst flags visible outside the class. diffstat: src/cpu/static_inst.hh | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diffs

Re: [m5-dev] Review Request: X86: Consolidate extra microop flags into one parameter.

> On 2010-08-23 06:59:18, Nathan Binkert wrote: > > Overall, I have to say that this is a much better way to do things. Did > > you consider using the Flags class in src/base/flags.hh? There are some > > examples of how it's used in sim/eventq.hh and mem/packet.hh. I'm not sure > > if it's

Re: [m5-dev] Review Request: ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/226/#review324 --- src/arch/arm/isa/insts/data.isa

Re: [m5-dev] Review Request: ARM: fixed a bug in the arm register flattening logic (FP_Base_DepTag was set too low)

> On 2010-08-23 11:29:37, Gabe Black wrote: > > src/arch/arm/registers.hh, line 77 > > > > > > Why was this added? I'm mostly just curious. Did something depend on > > it? I don't like the idea of constants trivially and consi

Re: [m5-dev] Review Request: ARM: Fix type comparison warnings in Neon

> On 2010-08-23 12:06:58, Nathan Binkert wrote: > > I asume that you have a meaningful commit message and that reviewboard > > screwed up. I don't want to be too anal here so feel free to overrule me, > > but is ltz a standard name in ARM? If not, perhaps we should try to > > standardize the

Re: [m5-dev] Review Request: ARM: Seperate the queues of L1 and L2 walker states.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/231/#review321 --- src/arch/arm/table_walker.hh

Re: [m5-dev] Review Request: ARM: Seperate the queues of L1 and L2 walker states.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/231/#review320 --- src/arch/arm/table_walker.hh

Re: [m5-dev] Review Request: ARM: Fix type comparison warnings in Neon

Strange, when I looked at the commit message the first time, it looked wrong, but now it seems fine. Whatever. On Mon, Aug 23, 2010 at 3:06 PM, Nathan Binkert wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > ht

Re: [m5-dev] Review Request: ARM: Fix type comparison warnings in Neon

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/220/#review319 --- Ship it! I asume that you have a meaningful commit message and that revie

Re: [m5-dev] Review Request: ARM: fixed a bug in the arm register flattening logic (FP_Base_DepTag was set too low)

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/227/#review318 --- You're commit message needs reformatting. The first line is much too long.

Re: [m5-dev] Review Request: CPU: Print out traces for faluting instructions when the flag for it (ExecFaulting) is set

> On 2010-08-23 11:01:56, Ali Saidi wrote: > > src/cpu/simple/atomic.cc, line 692 > > > > > > Well, the code needs to delete trace data and set it to null either > > way. Only if the execfaulting flag is set does it need to d

Re: [m5-dev] Review Request: ARM: Limited implementation of dprintf.

> On 2010-08-23 11:13:37, Gabe Black wrote: > > src/arch/arm/utility.cc, line 62 > > > > > > I realize the argument registers are just counting up from 0, but since > > you do define constants for them it might be better to pu

Re: [m5-dev] Review Request: ARM: Adding a bogus fault that does nothing. This fault can used to flush the pipe,

> On 2010-08-23 10:56:55, Gabe Black wrote: > > How about using the IsSerializing/IsSerializeAfter flags? I think that's a > > little different where code is fetched but stopped from going through > > decode, maybe, so those might not work. Otherwise the code looks fine. The > > first summary

Re: [m5-dev] Review Request: CPU: Print out traces for faluting instructions when the flag for it (ExecFaulting) is set

> On 2010-08-23 11:01:56, Ali Saidi wrote: > > src/cpu/simple/atomic.cc, line 692 > > > > > > Well, the code needs to delete trace data and set it to null either > > way. Only if the execfaulting flag is set does it need to d

Re: [m5-dev] Review Request: ARM: Exec traceflag prints out data for data instructions and some misc

> On 2010-08-23 10:49:21, Gabe Black wrote: > > Does this actually work? I thought traceData was set at the end when the > > registers were written out, so I would expect setting it while the > > instruction is processing its data would just get overwritten at that > > point. A less hacky (ISA

Re: [m5-dev] Review Request: ARM: Limited implementation of dprintf.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/228/#review311 --- src/arch/arm/utility.cc

Re: [m5-dev] Review Request: ARM: Adding a bogus fault that does nothing. This fault can used to flush the pipe,

> On 2010-08-23 10:56:55, Gabe Black wrote: > > How about using the IsSerializing/IsSerializeAfter flags? I think that's a > > little different where code is fetched but stopped from going through > > decode, maybe, so those might not work. Otherwise the code looks fine. The > > first summary

Re: [m5-dev] Review Request: CPU: Print out traces for faluting instructions when the flag for it (ExecFaulting) is set

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/233/#review309 --- src/cpu/simple/atomic.cc

Re: [m5-dev] Review Request: ARM: Remove ALPHA KSeg functions

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/229/#review308 --- Ship it! - Gabe On 2010-08-23 09:35:16, Ali Saidi wrote: > > -

Re: [m5-dev] Review Request: ARM: Adding a bogus fault that does nothing. This fault can used to flush the pipe,

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/230/#review307 --- How about using the IsSerializing/IsSerializeAfter flags? I think that's a

Re: [m5-dev] Review Request: ARM: Support unaligned memory access. Without this flag set,

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/232/#review306 --- Ship it! Looks good. - Gabe On 2010-08-23 09:34:32, Ali Saidi wrote: >

Re: [m5-dev] Review Request: CPU: Print out traces for faluting instructions when the flag for it (ExecFaulting) is set

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/233/#review305 --- src/cpu/simple/atomic.cc

Re: [m5-dev] Review Request: ARM: Exec traceflag prints out data for data instructions and some misc

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/234/#review304 --- Does this actually work? I thought traceData was set at the end when the

Re: [m5-dev] Review Request: ISA: Get rid of old, unused utility functions cluttering up the ISAs.

> On 2010-08-23 07:11:09, Nathan Binkert wrote: > > src/arch/alpha/ev5.cc, line 74 > > > > > > Is this all duplicate code? > > Gabe Black wrote: > I'm not sure why it was there. If I had to guess, I'd say it was moved > t

Re: [m5-dev] Review Request: ISA: Get rid of old, unused utility functions cluttering up the ISAs.

> On 2010-08-23 07:11:09, Nathan Binkert wrote: > > src/arch/alpha/ev5.cc, line 74 > > > > > > Is this all duplicate code? > > Gabe Black wrote: > I'm not sure why it was there. If I had to guess, I'd say it was moved > t

Re: [m5-dev] Review Request: CPU: Set a default value when readBytes faults.

> On 2010-08-23 07:18:06, Nathan Binkert wrote: > > memset and bzero are the same thing. I'd personally rather even see some > > thing like 0xAA in the memset so that we can see what happened. I've been told this was accidentally already committed, so I'll just replace bzero with memset(0xaa)

Re: [m5-dev] Review Request: ISA: Get rid of old, unused utility functions cluttering up the ISAs.

> On 2010-08-23 10:18:37, Ali Saidi wrote: > > src/arch/alpha/ev5.cc, line 74 > > > > > > This is all dead code? Are you sure? Yes. Mostly. :-) If you grep for the function name you'll see some hits, but those are CPUs defini

Re: [m5-dev] Review Request: ISA: Get rid of old, unused utility functions cluttering up the ISAs.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/213/#review299 --- src/arch/alpha/ev5.cc T

Re: [m5-dev] Review Request: X86: Create a directory for files that define register indexes.

> On 2010-08-23 07:12:58, Nathan Binkert wrote: > > In reviewboard, it just looks like you deleted a bunch of stuff, though I > > guess you actually did an "hg mv"? Yeah. In the patch itself those files all say something like this. diff --git a/src/arch/x86/apicregs.hh b/src/arch/x86/regs/apic

Re: [m5-dev] Review Request: ISA: Get rid of old, unused utility functions cluttering up the ISAs.

> On 2010-08-23 07:11:09, Nathan Binkert wrote: > > src/arch/alpha/ev5.cc, line 74 > > > > > > Is this all duplicate code? I'm not sure why it was there. If I had to guess, I'd say it was moved there to factor out its Alpha-n

Re: [m5-dev] Review Request: X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR.

> On 2010-08-23 07:03:46, Nathan Binkert wrote: > > src/arch/x86/types.hh, line 48 > > > > > > Do you really need to include this here, or can you just include it in > > the .cc file? Perhaps because of the template <>, you d

Re: [m5-dev] Review Request: ARM: Remove ALPHA KSeg functions

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/229/#review295 --- Ship it! I know that it says ARM:, but perhaps you should say something a

[m5-dev] Review Request: ARM: Expand the mode checking utility functions.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/217/ --- Review request for Default. Summary --- ARM: Expand the mode checking utility

[m5-dev] Review Request: ARM: Implement all ARM SIMD instructions.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/218/ --- Review request for Default. Summary --- ARM: Implement all ARM SIMD instructio

[m5-dev] Review Request: ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/219/ --- Review request for Default. Summary --- ARM: Implement CPACR register and retu

Re: [m5-dev] Review Request: ARM: Fix type comparison warnings in Neon

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/220/ --- (Updated 2010-08-23 09:38:55.088805) Review request for Default. Summary (updated

[m5-dev] Review Request: # HG User Gabe Black

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/220/ --- Review request for Default. Summary --- ARM: Fix type comparison warnings in N

[m5-dev] Review Request: ARM: Eliminate some unused enums.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/221/ --- Review request for Default. Summary --- ARM: Eliminate some unused enums. Di

[m5-dev] Review Request: ARM: Seperate out the renamable bits in the FPSCR.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/222/ --- Review request for Default. Summary --- ARM: Seperate out the renamable bits i

[m5-dev] Review Request: ARM: Fix VFP enabled checks for mem instructions

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/223/ --- Review request for Default. Summary --- ARM: Fix VFP enabled checks for mem in

[m5-dev] Review Request: ARM: Set the high bits in the part number so it's considered new by some code.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/224/ --- Review request for Default. Summary --- ARM: Set the high bits in the part num

[m5-dev] Review Request: ARM: Use less micro-ops for register update loads if possible.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/225/ --- Review request for Default. Summary --- ARM: Use less micro-ops for register u

[m5-dev] Review Request: ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/226/ --- Review request for Default. Summary --- ARM: Make VMSR, RFE PC/LR etc non spec

[m5-dev] Review Request: ARM: fixed a bug in the arm register flattening logic (FP_Base_DepTag was set too low)

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/227/ --- Review request for Default. Summary --- ARM: fixed a bug in the arm register f

[m5-dev] Review Request: ARM: Limited implementation of dprintf.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/228/ --- Review request for Default. Summary --- ARM: Limited implementation of dprintk

[m5-dev] Review Request: ARM: Remove ALPHA KSeg functions

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/229/ --- Review request for Default. Summary --- ARM: Remove ALPHA KSeg functions Dif

[m5-dev] Review Request: ARM: Adding a bogus fault that does nothing. This fault can used to flush the pipe,

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/230/ --- Review request for Default. Summary --- ARM: Adding a bogus fault that does no

[m5-dev] Review Request: ARM: Seperate the queues of L1 and L2 walker states.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/231/ --- Review request for Default. Summary --- ARM: Seperate the queues of L1 and L2

[m5-dev] Review Request: ARM: Support unaligned memory access. Without this flag set,

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/232/ --- Review request for Default. Summary --- ARM: Support unaligned memory access.

[m5-dev] Review Request: CPU: Print out traces for faluting instructions when the flag for it (ExecFaulting) is set

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/233/ --- Review request for Default. Summary --- CPU: Print out traces for faluting ins

[m5-dev] Review Request: ARM: Exec traceflag prints out data for data instructions and some misc

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/234/ --- Review request for Default. Summary --- ARM: Exec traceflag prints out data fo

[m5-dev] changeset in m5: BUILD: GCC 4.4.1/2 have a bug in their auto-vec...

changeset 47d9409b2b7f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=47d9409b2b7f description: BUILD: GCC 4.4.1/2 have a bug in their auto-vectorizer that we trip on diffstat: SConstruct | 8 1 files changed, 8 insertions(+), 0 deletions(-) diffs (18 lines

[m5-dev] changeset in m5: ALPHA: The previous O3 patch causes a slight st...

changeset aca917ca1ad5 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=aca917ca1ad5 description: ALPHA: The previous O3 patch causes a slight stats change with fullsys. diffstat: tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout|14 +- tests/long/

[m5-dev] changeset in m5: ARM: Exclusive accesses must be double word ali...

changeset aa32d1398dfd in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=aa32d1398dfd description: ARM: Exclusive accesses must be double word aligned diffstat: src/arch/arm/isa/insts/ldr.isa | 4 +++- src/arch/arm/isa/insts/str.isa | 4 +++- 2 files changed, 6 inserti

[m5-dev] changeset in m5: ARM: Add some registers for big loads/stores to...

changeset 24b18c320b66 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=24b18c320b66 description: ARM: Add some registers for big loads/stores to support neon. diffstat: src/arch/arm/registers.hh | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diffs (12 lines

[m5-dev] changeset in m5: ARM: Decode neon memory instructions.

changeset aabe621e58df in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=aabe621e58df description: ARM: Decode neon memory instructions. diffstat: src/arch/arm/isa/formats/fp.isa | 104 --- 1 files changed, 95 insertions(+), 9 deletio

[m5-dev] changeset in m5: Loader: Don't insert symbols into the symbol ta...

changeset 361b287b94b6 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=361b287b94b6 description: Loader: Don't insert symbols into the symbol table that begin wiht '$'. diffstat: src/base/loader/elf_object.cc | 8 ++-- 1 files changed, 6 insertions(+), 2 deletions

[m5-dev] changeset in m5: ARM: Clean up the ISA desc portion of the ARM m...

changeset 27dbb92bbad5 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=27dbb92bbad5 description: ARM: Clean up the ISA desc portion of the ARM memory instructions. diffstat: src/arch/arm/isa/insts/ldr.isa | 522 ++--- src/arch/arm/isa/

[m5-dev] changeset in m5: ARM: Add system for ARM/Linux and bootstrapping

changeset afbc40280b56 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=afbc40280b56 description: ARM: Add system for ARM/Linux and bootstrapping diffstat: src/arch/arm/ArmSystem.py| 18 ++ src/arch/arm/SConscript |1 + src/arch/arm/faults.cc |4

[m5-dev] changeset in m5: ARM: We don't currently support ThumbEE excepti...

changeset d6c8516b49e9 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=d6c8516b49e9 description: ARM: We don't currently support ThumbEE exceptions, so don't report that we do diffstat: src/arch/arm/isa.cc | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) d

[m5-dev] changeset in m5: ARM: Add configuration for Linux/Full System

changeset da93206873dc in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=da93206873dc description: ARM: Add configuration for Linux/Full System diffstat: configs/common/FSConfig.py | 58 ++ configs/example/fs.py | 31 +++

[m5-dev] changeset in m5: ARM: Change how the AMBA device ID checking is ...

changeset 177151a54462 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=177151a54462 description: ARM: Change how the AMBA device ID checking is done to make it more generic diffstat: src/dev/arm/RealView.py| 7 +- src/dev/arm/amba_device.cc | 21 +++

[m5-dev] changeset in m5: ARM: Add I/O devices for booting linux

changeset 28ddf6d9e982 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=28ddf6d9e982 description: ARM: Add I/O devices for booting linux diffstat: src/base/intmath.hh| 22 ++ src/dev/arm/RealView.py| 212 src/dev/arm/SConscript |

[m5-dev] changeset in m5: ARM: Implement some more misc registers

changeset 665d71561298 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=665d71561298 description: ARM: Implement some more misc registers diffstat: src/arch/arm/isa.cc | 23 ++ src/arch/arm/isa/formats/misc.isa | 3 ++ src/arch/arm/miscr

[m5-dev] changeset in m5: ARM: Fix an un-initialized variable bug

changeset a24f26bf0fbe in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=a24f26bf0fbe description: ARM: Fix an un-initialized variable bug diffstat: src/arch/arm/table_walker.cc | 10 ++ 1 files changed, 6 insertions(+), 4 deletions(-) diffs (35 lines): diff -

[m5-dev] changeset in m5: CPU: Set a default value when readBytes faults.

changeset 056a88043835 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=056a88043835 description: CPU: Set a default value when readBytes faults. This was being done in read(), but if readBytes was called directly it wouldn't happen. Also, instead of setti

[m5-dev] changeset in m5: Loader: Make the load address mask be a paramet...

changeset 6f77f379a594 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=6f77f379a594 description: Loader: Make the load address mask be a parameter of the system rather than a constant. This allows one two different OS requirements for the same ISA to be handled

[m5-dev] changeset in m5: Loader: Use address mask provided to load*Symbo...

changeset 692cdb71febd in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=692cdb71febd description: Loader: Use address mask provided to load*Symbols when loading the symbols from the symbol table. diffstat: src/base/loader/elf_object.cc | 8 src/base/loader/el

[m5-dev] changeset in m5: Compiler: Fixes for GCC 4.5.

changeset 4154f3e1edae in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=4154f3e1edae description: Compiler: Fixes for GCC 4.5. diffstat: src/arch/arm/table_walker.cc | 6 +++--- src/mem/cache/tags/iic_repl/gen.cc | 2 +- src/sim/serialize.cc | 4 +

[m5-dev] changeset in m5: BASE: Fix genrand to generate both 0s and 1s wh...

changeset 0002812cefe5 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=0002812cefe5 description: BASE: Fix genrand to generate both 0s and 1s when max equals one. previously was only generating 0s. diffstat: src/base/random.cc | 8 ++-- 1 files changed, 6

[m5-dev] changeset in m5: stats: Fix off-by-one error in distributions.

changeset f5742240963f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f5742240963f description: stats: Fix off-by-one error in distributions. bkt size isn't evenly divisible by max-min and it would round down, it's possible to sample a distribution and h

Re: [m5-dev] Review Request: CPU: Set a default value when readBytes faults.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/216/#review294 --- memset and bzero are the same thing. I'd personally rather even see some

Re: [m5-dev] Review Request: X86: Create a directory for files that define register indexes.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/215/#review293 --- In reviewboard, it just looks like you deleted a bunch of stuff, though I

Re: [m5-dev] Review Request: Power: Get rid of unused checkFpEnableFault.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/214/#review292 --- Ship it! - Nathan On 2010-08-22 19:01:23, Gabe Black wrote: > > --

Re: [m5-dev] Review Request: ISA: Get rid of old, unused utility functions cluttering up the ISAs.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/213/#review291 --- src/arch/alpha/ev5.cc I

Re: [m5-dev] Review Request: X86: Get rid of the flagless microop constructor.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/211/#review290 --- I see nothing obviously wrong with this. - Nathan On 2010-08-22 18:53:5

Re: [m5-dev] Review Request: X86: Make the TLB fault instead of panic when something is unmapped in SE mode.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/210/#review289 --- Ship it! Makes sense to me. (Though I don't know the code well) - Natha

Re: [m5-dev] Review Request: X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR.

> On 2010-08-23 07:03:46, Nathan Binkert wrote: > > Actually, can you use (UN)SERIALIZE_SCALAR? The commit message says that you can, but then you never use it. - Nathan --- This is an automatically generated e-mail. To reply, visit:

Re: [m5-dev] Review Request: X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/209/#review287 --- src/arch/x86/types.hh D

Re: [m5-dev] Review Request: X86: Consolidate extra microop flags into one parameter.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/205/#review286 --- Overall, I have to say that this is a much better way to do things. Did y

Re: [m5-dev] Review Request: CPU: Make the constants for StaticInst flags visible outside the class.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/204/#review285 --- Ship it! - Nathan On 2010-08-22 18:42:25, Gabe Black wrote: > > --

[m5-dev] Review Request: CPU: Set a default value when readBytes faults.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/216/ --- Review request for Default. Summary --- CPU: Set a default value when readByte

[m5-dev] Cron /z/m5/regression/do-regression quick

* build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.