Hi,
I am trying to simulate a benchmark developed using OpenCV 3.1 in
Syscall emulation mode.
OpenCV uses libpthread due to the use of locks, so I have to use
"m5threads" istead "libpthread" because Syscall emulatio mode can't
emulate the libpthread calls.
I can't use Full System mode beca
Hi Bhaskar,
To add to Jason's note -- if you are using ruby, you can create the tiled
topology you described by writing your own topology file.
Look at configs/topologies/MeshDirCorners for reference ...
You can connect your directory controller to a router and that router to other
routers or the
Hi All:
Thanks Andreas for drawing people's attention towards this issue. I've been
working on HMC for a while now and faced several issues that i mentioned in
my previous emails.
hmctest.py wroked just fine out of the box but only with traffic generators
(tgens). I modified HMC.py and hmctest.py
Hello Jason,
Thanks for your response. I am using the ruby cache and I am making change
in the "MESI_Two_Level". I want to create a 16 tile architecture where each
tile will have a CPU, a L1ICache, L1DCache, and a L2Cache which is shared
among all the cores. I have added a new component called "Ce
Hi Bhaskar,
If you are concerned with modeling interconnection networks you should use
Garnet, not the SimpleNetwork. Note: Both of these are part of Ruby, so you
have to use the Ruby caches, not the classic caches. Additionally, to
create at tiled architecture in Ruby will involve writing your ow
Hi,
I have encountered following problem while I was booting linux on armv7 noc.
./build/ARM/gem5.fast configs/example/fs.py
--machine-type=VExpress_GEM5_V1 --kernel
/home/khilji/gem5/m5/system/binaries/vmlinux --disk-image
/home/khilji/gem5/m5/system/disks/linux-aarch32-ael.img --dtb-filename
Hi Navin,
I would look at Process::allocateMem in src/sim/process.cc and brkFunc() in
src/sim/syscall_emul.cc. brkFunc is called every time the process exectute
the sbrk system call which increases the size of the heap. You could
probably modify Process::allocateMem to specify which virtual addres
Hello,
The SimpleCache in the tutorial is just an example of creating a memory
object. It is not meant to be used in simulation. It is not compatible with
the rest of gem5's caches, and it does not support any kind of cache
coherence. I'm surprised it worked at all in a two-level configuration, as
Dear all,
I'm trying to make my own cache object, which is finally used to simulate
the DRAM Cache using DRAMSim2.
This is my first time to modify gem5 code, so I have tried to make a simple
cache block to satisfy essential functions for a cache.
And I saw the tutorials and the sample code of Jas