Hi Alec,
Thanks for welcoming me!
What is current status in the implementation RISC-V FS mode?
Also, what are the open issues and where are you tracking them?
For now, I will check the above files pointed by you.
Thanks and Regards,
Rishabh Jain
On Fri, Mar 8, 2019 at 8:17 PM Alec Roelke
Hi All,
When I am running a lot of the SPEC '17 applications on gem5, I am getting
a warning message that says *warn: instruction 'movntdq_Mo_Vo'
unimplemented*. The source code for the binary does not seem to indicate
the usage of the movntdq instruction.
I assume it is the glibc that is using
Hi Jason,
Is there support for Mevbench benchmark suite in gem5-gpu, say if I want to
configure an integrated cpu-gpu system?
Regards,
Abhishek Bhattacharyya
Graduate Research Assistant
Electrical and Computer Engineering Department
University of Wisconsin-Madison
Hi,
A smart way to know how many instruction to Fastforward is to use dump
stats just after boot up for the first run and then see instruction count.
Second way is to use checkpointing technique for the boot-up and then
restore from that and then run your application.
For monitoring accesses I
Hi Abhishek,
I wonder if you are using the default CPU configuration for full-system or
do you have any changes?
Regards
-Ayaz
On Wed, Mar 6, 2019 at 2:20 PM Abhishek Singh <
abhishek.singh199...@gmail.com> wrote:
> Hello Everyone,
>
> I am trying to run the gem5 full system with X86 ISA and
The RISC-V CSRs are implemented as misc regs, which are the responsibility
of the ISA to maintain. ISA traits for RISC-V are implemented in
src/arch/riscv/isa.cc and .hh. The ISA object itself does not have any
references to CPUs or threads, so CSRs such as performance counters and
MHARTID can't
