Re: [gem5-users] Fw: [gem5]: SHA2 and SHA3 on gem5

You can refer to Syscall Emulation mode on gem5's documentation page if you would like to run any binary programs. The documentation page should be thorough enough. Cheers, Libo -- Original -- From: "ABD ALRHMAN ABO ALKHEEL";; Send time: Friday, Oct 18, 20

Re: [gem5-users] Fw: [gem5]: SHA2 and SHA3 on gem5

Hi, thanks for your email. It basically hash algorithm. Please have a look at this link https://github.com/brainhub/SHA3IUF . How I can run this algorithm on gem5? From: gem5-users on behalf of Abhishek Singh Sent: Thursday, October 17, 2019 8:43:23 PM To: gem5

Re: [gem5-users] Fw: [gem5]: SHA2 and SHA3 on gem5

Hi, thanks for your email. It basically hash algorithm. Please have a look at this link https://github.com/brainhub/SHA3IUF . How I can run this algorithm on gem5? From: gem5-users on behalf of Abhishek Singh Sent: Thursday, October 17, 2019 8:43:23 PM To: gem5

Re: [gem5-users] Fw: [gem5]: SHA2 and SHA3 on gem5

Hi, Can you explain in detail what is SHA2 and SHA3, any links? On Thu, Oct 17, 2019 at 3:09 PM ABD ALRHMAN ABO ALKHEEL < abdkeel...@hotmail.com> wrote: > Hello everyone, > > I wanna run the sha3 and sha2 on gem5. I need your help. > > Best Regards > -- > *From:* ABD A

[gem5-users] Fw: [gem5]: SHA2 and SHA3 on gem5

Hello everyone, I wanna run the sha3 and sha2 on gem5. I need your help. Best Regards From: ABD ALRHMAN ABO ALKHEEL Sent: Thursday, October 17, 2019 3:00:35 AM To: gem5 users mailing list Subject: [gem5]: SHA2 and SHA3 on gem5 Hello everyone, I wanna run the s

Re: [gem5-users] Memory Command

Hi yuan, There is no document detailing those commands except few comments in packet.hh file. Whatever commands you are confused about please reply to this email thread, so that everyone whoever has any knowledge will start sharing and then we can combine it and put it as a document. On Fri, Oct

Re: [gem5-users] Adding latencies in cache accesses

Hi Vector, You need to search for fill latency in src/mem/cache/base.cc and response latency in src/mem/cache/cache.cc in serviceMSHR function call. On Wed, Oct 16, 2019 at 5:38 PM Victor Kariofillis wrote: > Hi Daniel, > > First of all thanks for answering. I have some more questions. In my cas

[gem5-users] (no subject)

Hi, I'm trying to run multiworkload smt. I an the hello world program from tests, and I see that one of the outputs is displayed after m5exit. What is the reason for this? ./build/X86/gem5.opt ./configs/example/se.py --smt --cpu-type=DerivO3CPU --caches -c tests/test-progs/hello/bin/x86/linux/he

[gem5-users] Problem with DerivO3CPU and Ruby in FS

Hello All, Could someone please confirm whether DerivO3CPU with Ruby are working properly? I have been having the same problem with both X86 and ARM when running a multithreaded application (a simple hello world program with 2 threads) on DerivO3CPU and Ruby. After some time I get an assertion fa

Re: [gem5-users] Delayed printing to telent localhost 3456

Just an update: It seems that the problem is not there or at least not as severe when I used the aarch64-ubuntu-trusty-headless.img disk image. My previous experiments were using the linaro-minimal-aarch64.img disk image. I am not sure what makes the difference between both images. On Fri, Oct 4,

Re: [gem5-users] FW: Running Dhrystone on GEM5

On 10/17/19 10:02 AM, Javed Osmany wrote: > *From:*Javed Osmany > *Sent:* 16 October 2019 07:15 > *To:* gem5-users-requ...@gem5.org > *Cc:* Javed Osmany > *Subject:* FW: Running Dhrystone on GEM5 > > *From:*Javed Osmany > *Sent:* 15 October 2019 17:54 > *To:* gem5-users-requ...@gem5.org

[gem5-users] FW: Running Dhrystone on GEM5

From: Javed Osmany Sent: 16 October 2019 07:15 To: gem5-users-requ...@gem5.org Cc: Javed Osmany Subject: FW: Running Dhrystone on GEM5 From: Javed Osmany Sent: 15 October 2019 17:54 To: gem5-users-requ...@gem5.org Cc: Javed Osmany mailto:javed.osm...@huawe

[gem5-users] Correction: TLB timing model in x86 SE O3CPU

Hello Everyone and Gabe, Does x86 gem5 SE mode using O3CPU considers timing delays of TLB Hit and TLB miss? If yes, which file has it? I could not find any timing parameter in src/arch/tlb.cc in translate timing function Is that timing delay overlapped with the cache access timing delay? Also,

[gem5-users] TLB timing model in x86 SE Mode

Hello Everyone, Does x86 gem5 SE mode considers timing delays of TLB Hit and TLB miss? If yes, which file has it? I could not find any timing parameter in src/arch/tlb.cc in translate timing function Is that timing delay overlapped with the cache access timing delay? Also, how is the tlb functi