[gem5-users] Run Apk files on Gem5

Hello Everyone, I wanna run apk files on gem5 with arm. I don’t have any idea about that. Any help would be appreciated. Best Regards ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Simulation does not stop, SE mode, 2 cpus, DerivO3CPU, ruby memory

Hi Arun, My bad the issue is still there Best regards, Abhishek On Mon, Mar 2, 2020 at 12:57 AM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hi Arun, > > I tested gem5_19 with classic cache x86 with O3CPU, both smt and multicore > simulations are working > > Best regards, > > Abh

Re: [gem5-users] Simulation does not stop, SE mode, 2 cpus, DerivO3CPU, ruby memory

Hi Arun, I tested gem5_19 with classic cache x86 with O3CPU, both smt and multicore simulations are working Best regards, Abhishek On Mon, Mar 2, 2020 at 12:34 AM Arun Kavumkal wrote: > Hi Ciro > I was debugging the X86, mutlticore issue as suggested by you. > I could see that the simulation

Re: [gem5-users] Simulation does not stop, SE mode, 2 cpus, DerivO3CPU, ruby memory

Hi Ciro I was debugging the X86, mutlticore issue as suggested by you. I could see that the simulation exits as expected by changing * if (activeContexts ==0)* at https://github.com/gem5/gem5/blob/9fc9c67b4242c03f165951775be5cd0812f2a705/src/sim/syscall_emul.cc#L212 to *if (activeContexts == 1).*

Re: [gem5-users] Question about CacheLoad/StorePorts

Hi, The configuration in source code are not decided depending on any specific architecture. One needs to change it depending on what architecture they are targeting. If you read papers who have used gem5, they always target a particular architecture (skylake, coffee lake, or any and or arm, etc)

[gem5-users] Question about CacheLoad/StorePorts

Hello all, I ran into a question while looking through the `cacheLoadPorts` and `cacheStorePorts` variable in `src/cpu/o3/O3CPU.py`[1]. The default values are set to 200, and a search through GitHub shows that this default value seems to be always used. (At least for the provided example configur

Re: [gem5-users] RISC-V non-branch instructions detected as a branch

Hi, As a follow-up to my previous email, I think I know what causes the problem, but I don't know how to solve it. The source of the problem seems to be that the value of the private variable _compressed of RISC-V PCState objects is not set properly. In other words, I couldn't find any place in t

Re: [gem5-users] Commit numbers/tags of previous stable version missing

Thank you Bobby for your reply. I just found all the tags in my old repos and saved them. On Sun, Mar 1, 2020 at 11:50 AM Bobby R. Bruce wrote: > Abhishek, > > I’m not aware of any tags that were previously used to mark stable > versions. As far as I know, gem5-19 is the first stable release.

Re: [gem5-users] Commit numbers/tags of previous stable version missing

Abhishek, I’m not aware of any tags that were previously used to mark stable versions. As far as I know, gem5-19 is the first stable release. If patches were made to previous versions of the product then I suspect they were made to arbitrary revisions, in which case I’d advise getting in contac

Re: [gem5-users] Modifying source code in gem5

Could you give me more details? Where did you add the cprintf()? Which command are you using for running gem5? If you want to modify the gem for test purposes, I suggest inserting the cprintf() in the tick() method because this method is always called in the O3CPU model. I guess you might add t

[gem5-users] Commit numbers/tags of previous stable version missing

Hello everyone, Can anyone provide me with the commit number of the previous stable version of gem5? This stable-tags has been removed recently like 3 days before. *Bobby and Jason*: Is there any reason for removing it? I am asking this because there are other simulators (mostly from Prof. Onur

[gem5-users] Modifying source code in gem5

I’m trying to modify source code in gem5. For testing, I add a cprintf() statement to src/cpu/o3/fetch_impl.hh. Then using scons, I rebuild gem5. But, any change didn’t happen. What did I miss? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.