Hello Giacomo,
Thank you for your help.
After doing what you proposed I tested perf and directly reading the counters
but still the eventcounters work but the cyclecounter is always zero. I double
check the implementations with known one from the literature, and also I read
the gem5 console to s
The problem seems to be caused by the m5.cpt in the checkpoint I acquired
not having arm-sve tag and vecPredRegs. However, if I run cpt_upgrader.py
on the checkpoint, it adds the arm-sve tag without doing anything about the
absence of vecPredRegs. Does anyone know a workaround without reverting my
Hey Srikrishna,
I had a look into this for you. Turns out we still had an old gem5
mercurial repo hanging around for us to see where this patch goes. To apply
this patch on our git repo you'll need to checkout revision
6498ccddb2f13a6fac6a210372b1aa86873507b9, then use `git apply` with the
`--whit
> -Original Message-
> From: POLYCHRONOU Nikolaos
> Sent: 19 November 2020 12:04
> To: gem5 users mailing list ; Giacomo Travaglini
>
> Subject: RE: [gem5-users] Re: Using perf_event with the ARM PMU inside gem5
> on Linux
>
> Hello Giacomo,
>
> So apparently it works when I don't defin
Hello fellow gem5 users,
I recently started using gem5 again, and my current question relates to
the current best practice to generate ARM checkpoints using simpoints.
Specifically, even by generating BBV files (used by simpoints) for
SPEC2k17 binaries through a fast mechanism, dumping checkp
gem5 does not use mercurial any more and hasn't for a while, and so using
hg commands probably won't work. You should be able to apply the patches
using the normal "patch" command, or even with git using the "git am"
command, but if your patches are really old (likely if they're geared
towards merc
In what way was it not possible? Did you get an error message?
Gabe
On Wed, Nov 18, 2020 at 1:51 PM Cristobal Ramirez Lazo via gem5-users <
gem5-users@gem5.org> wrote:
> Dear all,
> I would like to use the m5ops functions such as "m5_reset_stats" in my own
> c++ program.
> I have done it for x86
Hi,
The files you want to look at for the memory access are src/mem/
dram_ctrl.cc/.hh and src/mem/DRAMCtrl.py for issuing requests from the
memory controller. The memory access itself is performed in
DRAMCtrl::accessAndRespond, with a call to access() which is defined in
src/mem/abstract_mem.cc.
Hello Giacomo,
So apparently it works when I don't define the --dtb as an option. Quite funny
I thought you need to add this option necessarily.
I will test if now my scripts are running.
I want some guidance on how to implement the
> > Have you defined a probe point in the icache/bpred?
> > You
Okay I will check this out.
For the add of probes it is also added in the addPMUs?
For example I see this in the comments of the addPMUs
> :type ints: List[int]
> :param events: Additional events to be measured by the PMUs
> :type events: List[Union[ProbeEvent, SoftwareInc
> -Original Message-
> From: POLYCHRONOU Nikolaos
> Sent: 19 November 2020 11:03
> To: Giacomo Travaglini ; gem5 users mailing
> list
> Subject: RE: [gem5-users] Re: Using perf_event with the ARM PMU inside gem5
> on Linux
>
> For the dtb i use the following armv8_gem5_v1_1cpu.dtb
>
T
For the dtb i use the following armv8_gem5_v1_1cpu.dtb
Fot the configs/example/arm/devices.py? i do the following modifications:
def addPMUs(self, ints, events=[]):
"""
Instantiates 1 ArmPMU per PE. The method is accepting a list of
interrupt numbers (ints) used by the
> -Original Message-
> From: POLYCHRONOU Nikolaos
> Sent: 19 November 2020 10:25
> To: gem5 users mailing list
> Cc: Giacomo Travaglini
> Subject: RE: [gem5-users] Re: Using perf_event with the ARM PMU inside gem5
> on Linux
>
> Hello and thank you for your answer,
> Yes I write assem
Hello and thank you for your answer,
Yes I write assemply language to instantiate the counters. I don't bother with
perf even if I tried to access the cycle counter but the file descriptor didnt
open.
static int perf_fd_cpu_cycles;
static struct perf_event_attr attr_cpu_cycles;
attr_cpu_cyc
Hi Nikolaos
> -Original Message-
> From: POLYCHRONOU Nikolaos via gem5-users
> Sent: 18 November 2020 07:20
> To: gem5-users@gem5.org
> Cc: POLYCHRONOU Nikolaos
> Subject: [gem5-users] Re: Using perf_event with the ARM PMU inside gem5 on
> Linux
>
> Helllo.
>
> I encounter the following
15 matches
Mail list logo