[gem5-users] Re: Slowness when running SAT Solver in gem5 SE mode

Umm, it's a simulator, and you requested the most detailed simulation mode (DerivO3CPU). I expect slowdown factors of *at least* 1000 with such a mode. That you are seeing perhaps 4000-5000 does not surprise me all that much. The simulator has to do a lot of work for each simulated instruction.

[gem5-users] Re: SPEC CPU2017 X86 SE mode - instruction 'palignr_Vdq_Wdq_Ib' unimplemented

Hi Eliot and Abitha, After Eliot's advice, I also tried to compile spec using the flags you used, and also "-march=nocona". Unfortunately, inspecting the generated assembly, I see that the "palignr" instruction is always present. I'll update you if I manage to compile the binaries without usi

[gem5-users] Re: SPEC CPU2017 X86 SE mode - instruction 'palignr_Vdq_Wdq_Ib' unimplemented

Hi Eliot and Mirco, I had the same issue with \`palignr_Vdq_Wdq_Ib\` being unimplemented. I tried compiling my application binary (i.e., the one I was trying to run on gem5, not gem5 itself) to exclude SSE which contains that instruction. I used gcc flags \`-mno-sse3 -mno-ssse3 -mno-sse4.1 -mno

[gem5-users] Slowness when running SAT Solver in gem5 SE mode

Hello, I am currently working on a project that aims at analyzing the differences in SAT/SMT solver performance on benchmarks (IPC/cache misses/branch misses) when varying architectural aspects of a CPU (cache size, associativity, etc). I figured that to begin testing, I would implement a baseline

[gem5-users] Re: Determine the number of pipeline stages

Hi Haseung, Thank you for your quick reply! I am actually using the TimingSimpleCPU and the MinorCPU, but I just saw that in the manual you pointed out there is a section for each of the models. Thank you a lot! :) Kind regards, Joao Vieira On 13/03/23 17:05, 봉하승 wrote: Hi Joao, If it is

[gem5-users] Re: Determine the number of pipeline stages

Hi Joao, If it is an in-order, is it implemented by changing all path widths to 1 using o3cpu? Or did you use AtomicSimpleCPU, TimingSimpleCPU, MinorCPU? If your cpu-type is o3cpu, The basic pipeline configuration is shown in the link below. https://www.gem5.org/documentation/general_docs/cpu_mo

[gem5-users] Gem5 SE - TLM Seg Fault MemPool::FreePageAddr

Hi All, I am trying to simulate a scenario where I want a TimingSimpleCPU connected to a TLM memory and this is causing a segfault in gem5::MemPool::freePageAddr. Can you help me understand/progress from this issue? I followed the instructions in util/tlm/README as follows: In util/tlm 1. ../..

[gem5-users] Determine the number of pipeline stages

Hi, I am taking some performance results using In-Order x86, ARM, and RISC-V CPUs in gem5, and I was wondering where to find the number of implemented pipeline stages for each architecture. I have looked into the simulation output files and I am having some difficulty locating this informatio

[gem5-users] Re: gem5 / garnet / simple custom routing

Yes, when I simulate the topology with the default weight-based routing algorithm it's working fine. and the simulation ends when the network tester completes simCycles successfully. Actually I can't tell exactly when the segmentation fault happens, but it's happening the moment when I hit the sim

[gem5-users] Re: gem5 / garnet / simple custom routing

Hi Karim, Where does the segfault happen? Have you tried your topology with the default weight-based routing algorithm? Regards, Gabriel ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org