[gem5-users] What is the requirement for cache?

Dear all, I'm trying to make my own cache object, which is finally used to simulate the DRAM Cache using DRAMSim2. This is my first time to modify gem5 code, so I have tried to make a simple cache block to satisfy essential functions for a cache. And I saw the tutorials and the sample code of Jas

[gem5-users] Is the gem5 stable version supported continuously?

As I see, the latest stable version is 2015.09.03. And it is very different with recently public gem5. Is the gem5 stable version supported continuously? If not, and I need to use recent public gem5, could it be problem due to frequent code change? ___

Re: [gem5-users] Small entry table creation in gem5

Hello. I think it depends on the purpose of the table and modeling features. For example, let's look a cache tag modeling case. BaseTags class (/mem/cache/tags/base.hh), which is a kind of table to store tags, inherits the ClockedObject, because BaseTags needs to model the clock latency. However

[gem5-users] Read error, exit when run mcf of spec2006

Hi all, I am trying to test my new cache scheme in gem5, but when I try to run the 429.mcf of spec2006, there is a error to load a file (maybe inp.in). The other benchmarks of spec2006 are run well. I saw the similar previous case in the below link. http://thread.gmane.org/gmane.comp.emulators.m5

[gem5-users] How can I use Write Through Cache

Hi all, I have two questions. First, as I know, in gem5, there is only write-back cache. Is it alright? Second, if there is only write-back cache, for implementation, how can I approach to implement a write-through cache? Thanks. Haeyoon Cho ___ gem5

[gem5-users] The learning gem5 code can't be compiled.

Hi all, The recent commit for learning gem5 occurs a compile error. The cause is #include base/misc.hh, because misc.hh is renamed to logging.hh recently. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-use

Re: [gem5-users] Implementing tag-less cache architecture only for the last level cache

Dear, Varun. In my opinion, you can make new class which inherit BaseCache or MemObject. As I think, if you implement tag-less cache in conventional cache class, you need to a flag which indicate tag-less cache and many conditional sentence everywhere operate differently with a conventional cache

Re: [gem5-users] Configuration visualizer

Dear, Timon Install pydot, and then rebuild gem5 and run simulation. Then, you can see config.dot.pdf file which has the content like below. [image: 본문 이미지 1] Best regards Haeyoon Cho 2018-01-03 23:06 GMT+09:00 Timon Evenblij : > Hi all, > > I thought I once came across a tool to visualize the

[gem5-users] DRAMCtrl parameters for DDR4_2400_8x8

Dear, all. According to below link, http://repo.gem5.org/gem5?cmd=changeset;node=17b37f38944a DDR4_2400_8x8 uses a 8-bit width device and 8 devices are in a rank. My doubt is the below. DDR4_2400_8x8 class is overriding DDR4_2400_16x4 class in DRAMCtrl.py However, the devices_per_rank is still

[gem5-users] Is the dtb file important for FS simulation?

Dear, everyone. I try to full system simulation for ARM ISA. So, I downloaded the pre-compiled kernels and disk images (aarch-system-20170616.tar.xz) from the repository ( http://www.gem5.org/dist/current/arm/). There are several dtb files like below. vexpress-v2p-ca15-tc1-gem5_1cpus.20170616.dtb

Re: [gem5-users] Is the dtb file important for FS simulation?

tion. > > > > Normally the original source of the dts for ARM should be present on > > the forked gem5 Linux kernel fork: > > https://gem5.googlesource.com/arm/linux/+/917e007a4150d26a0aa95e4f5353ba > 72753669c7/arch/arm/boot/dts/ > > but I can't find if ea

[gem5-users] Question about multi-core simulation exit timing.

Dear, all. As I know, there are two exit timing variable in the BaseCPU.py which are max_insts_all_threads and max_insts_any_thread. But, it is a limitation of a single core. I want to exit the multi-core simulation by total executed instructions across all core. How can I do? Best Regards, Hae

Re: [gem5-users] how to compile hello.c of the linaro image with "Cross-Compile" and execute it in gem5.

First, cross compile hello.c. It is not dependent on gem5. Second, mount the linaro image and copy the binary file. For example, mount -oloop,offset=32256 /tmp/linaro.img /mnt Finally, run the FS simluation. http://gem5.org/Running_gem5 2018-05-13 20:28 GMT+09:00 commerce _com : > hi all; > >

Re: [gem5-users] Terminating multi-core simulation

Dear Avais, I think running workloads fairly is very important in multi-core experiments, because the number of executed instructions of each core can be changed depend on each experimental configuration. There is a prior work how to experiment fairly on multi-core system; A. Hilton et al., "FIEST

Re: [gem5-users] Terminating multi-core simulation

t; I have one more question, is it good idea to normalize the stats with > number of instructions simulated to calculate energy or other things? Does > people use this? Or some other metric to compare energy? > > Many thanks for your help, > Best Regards, > Avais > > On Thu, May

Re: [gem5-users] Error in running Moby(Asimbench) benchmark in gem5

Dear Mitali Sinha. In my case, I run moby bench with RealView_PBX machine type. I don't know if it is the cause, but give it a try. Best Regard, Haeyoon Cho. 2018-05-29 20:39 GMT+09:00 Mitali Sinha : > I have followed the instructions provided in the gem5.org website to run > the Moby benchmark

Re: [gem5-users] Error in running Moby(Asimbench) benchmark in gem5

libc.so.6(__libc_start_main+0xf0)[0x7f5eb5686830] > build/ARM/gem5.opt(_start+0x29)[0x8f6e19] > --- END LIBC BACKTRACE --- > Aborted (core dumped) > > > > I don't know if I am doing it correctly. Also I am not sure if I am using > the correct dtb files and boot_emm.arm files

Re: [gem5-users] Error in running Moby(Asimbench) benchmark in gem5

I found what is the problem. The cause is not a dtb file. It is --mem-size. You need to specify the unit of the capacity (MB or GB). As I think, it is due to the lack of memory size. 2018-06-05 17:43 GMT+09:00 조해윤 : > Dear Mitali Sinha. > > Sorry for late reply. > Try it without s

Re: [gem5-users] The simulator can't read the contents of the rcS file

Dear Jung Min You. The command line looks fine. How did you write the script? The hack_back_ckpt.rcS is basically for checkpoint. This script detect itself whether is was run before, in other words, the simulation was restored by the checkpoint. Thus, depend on the position of the echo command in

Re: [gem5-users] The simulator can't read the contents of the rcS file

e, the echo statements didn't print on the > terminal. > > As the echo statement located at the first line, I think it must be > printed. > > Thanks. > > Best regards, > > Jung Min. > > > 2018-06-08 15:50 GMT+09:00 조해윤 : > >> Dear Jung Min You.

Re: [gem5-users] The simulator can't read the contents of the rcS file

ch I type > command lines. > > By the way, what do you mean boot? > > Do I need to boot gem5 to use script file? > > Best regards, > > Jung Min You > > 2018-06-08 16:43 GMT+09:00 조해윤 : > >> Dear Jung Min You. >> >> It is strange. Is it booted well? &

[gem5-users] How can I run the Ligra framework in gem5 x86 SE mode?

Dear. all. As a graph analysis benchmark suite, I'm considering the Lirga framework which is multi-thread program using the OpenMP. I found the paper (A. Addisie, et al., "Heterogeneous Memory Subsystem for Natural Graph Analytics," IISWC, 2018) which run Ligra on x86 SE mode, so running Ligra on

[gem5-users] m5threads compile error

Dear. all I'm trying to compile m5threads. At the m5threads directory, when I run the command gcc -static -c pthread.c -o pthread.o the error occurs like below. pthread.c: In function ‘pthread_create’: pthread.c:256:3: warning: implicit declaration of function ‘clone’; did you mean ‘close’? [-W