[gem5-users] Content of a cpu cache line

Hi everyone, Please i would like to know which class is representing a cache line in gem5. The cacheBlk class seems to represent only a part of the CPU cache line. I would actually like to display the contents of a cache line for analysis. Kind regards. *JEATSA TOULEPI Armel* Ingénieur infor

[gem5-users] Sharing data from a cache line between several processes.

probably *YES*, but i want to be sure about that. regards, Armel. *JEATSA TOULEPI Armel* Ingénieur informaticien Tel: +237 650771894 / 655296800 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Full system simulation freeze

Hello, Yes but i use TimingSimpleCPU. kind regards, Armel. -- *JEATSA TOULEPI Armel* Étudiant En Génie Informatique Tel: +237 650771894 / 655296800 Le lun. 22 juil. 2019 à 01:20, Gabe Black a écrit : > Hi. Simulations with the KVM CPUs run on actual hardware and are only as > determi

Re: [gem5-users] Full system simulation freeze

* upwards the simulation does not end (*or takes very very long time but i don't know because i stopped the simulation after 2 hours*). It is as if the simulation time increases exponentially with the number of CPUs. kind regards, Armel -- *JEATSA TOULEPI Armel* Étudiant En Génie Informatiqu

Re: [gem5-users] Full system simulation freeze

Hello, Thank you for your reply. I will try the patch. I think the command line is deterministic. I realized that when I set the number of cpu to 1 or 2, the simulation runs normally but from 3 it freezes in line *"brought up x cpu"*. kind regards, Armel. -- *JEATSA TOULEPI Armel* É

Re: [gem5-users] Full system simulation freeze

* and it seems to freeze at line : *"Brought up 4 CPUs"* kind regards, Armel -- *JEATSA TOULEPI Armel* Étudiant En Génie Informatique Tel: +237 650771894 / 655296800 Le lun. 15 juil. 2019 à 17:22, Jason Lowe-Power a écrit : > Hi Armel, > > It's unlikely the performance o

[gem5-users] Full system simulation freeze

oblem?? could it be related to the performance of my machine? Kind regards, Armel. -- *JEATSA TOULEPI Armel* Étudiant En Génie Informatique Tel: +237 650771894 / 655296800 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Design of an unified instruction cache

;*mostly_excl*' sufficient for this? kind regards, Armel -- *JEATSA TOULEPI Armel* Étudiant En Génie Informatique Tel: +237 650771894 / 655296800 Le mer. 10 juil. 2019 à 18:35, Armel Jeatsa a écrit : > Thank you very much for your replies. > I will start using classic caches since i do

Re: [gem5-users] Design of an unified instruction cache

Thank you very much for your replies. I will start using classic caches since i do not have to modify coherance protocol for my work. kind regards, Armel -- *JEATSA TOULEPI Armel* Étudiant En Génie Informatique Tel: +237 650771894 / 655296800 Le mer. 10 juil. 2019 à 18:11, Jason Lowe-Power a

[gem5-users] Design of an unified instruction cache

Hello, I am relatively new in gem5 simulator, i have to design a multiprocessor architecture with two levels of caches composed of: - At level 1: the usual L1i and L1d caches - At level 2 (shared by all processors): L2i and L2d caches, L2i inclusive with L1i, and L2d non-inclusive with L1