Hello all,
I have been able to boot newer and unmodified x86 kernels after doing a bit of
research and debugging, I managed to get a 3.2.24 kernel to work.
One of the main issues was the SMP initialization with the "trampoline" code.
This is the very first routine that any slave processor execu
: viernes, 15 de agosto de 2014 0:26
Para: Castillo Villar, Emilio; gem5-users@gem5.org
Asunto: Re: [gem5-users] Problem in assigning clock to L1 cache in Ruby
I used MESI Two Level with the detailed cpu model, fs and X86 for 64 node and
changing the cpu frequency dynamically (DFS) successfully
: parisa khadem hamedani [parisahamed...@gmail.com]
Enviado: jueves, 14 de agosto de 2014 21:26
Para: Castillo Villar, Emilio; gem5-users@gem5.org
Asunto: Re: [gem5-users] Problem in assigning clock to L1 cache in Ruby
Hi Emilio,
I am using X86_MESI_Two_Level for full system simulation of lu_cb
Can you specify the cmdline and protocol that you are using?
Enviado desde mi iPad
El 14/08/2014, a las 00:34, "parisa khadem hamedani via gem5-users"
mailto:gem5-users@gem5.org>> escribió:
Hello,
In Ruby, L1 and L2 caches are employing the Ruby clock. However I need the L1
cache uses the cp
You can only take checkpoints with MOESI Hammer. If you're having errors they
might be some unresolved bugs in your gem5 version.
De: Choi, Wonje [wonje.c...@email.wsu.edu]
Enviado: sábado, 21 de junio de 2014 10:30
Para: Castillo Villar, Emilio;
Hello
Ruby deadlocks right after taking a checkpoint. Despite the checkpoint being OK.
Once the simulation is checkpointed you have to stop the simulation and start
it again from the checkpoint.
De: gem5-users [gem5-users-boun...@gem5.org] en nombre de Ch
.@gmail.com]
Enviado: domingo, 08 de junio de 2014 23:27
Para: Castillo Villar, Emilio
CC: Ivan Stalev; gem5 users mailing list
Asunto: Re: [gem5-users] System Hangs
Hi guys,
I've been able to reproduce Ivan's issue in the latest gem5 (rev. 10235). It
seems this may be the same bug as a re
Hello,
I have seen similar issues when running X86 timing and detailed cpus with the
Classic memory system. Mostly due to X86 atomic memory accesses not being
implemented. The stdout freezes but instructions are still being committed.
If you want to run with timing or detailed cpus in X86 & FS
Hello,
The classic memory model does not support the atomic memory accesses that X86
does.
In FS you will have many situations where this behavior can be exposed, doing a
simple cat /proc/cpuinfo will hang the simulation. The chances of your
benchmark getting stuck are quite high. However I hav
The sleep is delaying the simulator, NOT the simulation,
If you want the simulated workload to take longer you have to figure out how to
stall the cpu.
Playing with cache latencies should do the trick.
De: gem5-users-boun...@gem5.org [gem5-users-boun...@gem
Hello
[NetDest (3) 0 1 0 0 - 1 1 0 0 - 0 0 - ] Is a bit mask specifying the
controller the packet is bound for,
I believe the first 4 0s is the L1 controller, it will be the L1 controller
with id 2. (2nd bit set to 1).
Then the L2 controllers with ids 0 and 1, the last two bits are the direc
RV: Getting an invalidation request with no
destination.
Castillo Villar, Emilio unican.es> writes:
>
> Good evening
I ran the experiment also got the result as you post.
NI:22 Injecting msg [RequestMsg: Addr = [0x98ad80, line 0x98ad80] Type =
INV AccessMode = User Request
I was having a similar problem, the PID was not always being read properly and
got some address translation errors as well.
In the end I added a m5 pseudo instruction to store the running pid in a
register.
I call this pseudo inst from the kernel each time it does a context switch.
kernel/sched
Dear all,
I have been trying to boot a kernel >= 2.6.33 without any success. After a few
days looking at the issue I got some hints on what may be happening.
When the OS boots an idle core, it sends the core an interruption with a memory
address pointing to a trampoline code.
Until version 2.6
Hello,
at the output directory you have all the std output of the simulated machine in
a file ".terminal"
De: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] en nombre de
Christian Menard [christian.men...@tu-dresden.de]
Enviado: viernes, 07 de
Hello,
I am trying to do something similar where each core has it's own clock,
To do this I'm creating a ClockDomain per core in the fs.py script.
Looking like:
test_sys.cpu_clk_domain = SrcClockDomain(clock = "2GHz",
voltage_domain =
Ruby checkpointing is protocol independent.
You must take the checkpoint using MOESI_hammer,
then you can restore it with any other protocol.
De: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] en nombre de
zen...@ict.ac.cn [zen...@ict.ac.cn]
Enviado e
Hello,
You have a nice description at the wiki:
http://gem5.org/O3CPU
Kind regards
De: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] en nombre de
tareq ALAWNEH [tareqalawneh1...@yahoo.com]
Enviado el: martes, 05 de noviembre de 2013 9:57
Para: gem5-u
this?
Thanks a lot for your time,
Kind regars.
De: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] en nombre de
Castillo Villar, Emilio [emilio.casti...@unican.es]
Enviado el: viernes, 01 de noviembre de 2013 15:06
Para: m5-us...@m5sim.org
Asunto:
Yes, you can
in the network, the NetDest entries will be iterated, and a packet for each of
the destinations will be generated.
Regards,
Emilio Castillo
De: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] en nombre de Alex
Tomala [alegomas...@yahoo.ca
Good afternoon,
I am doing some experiments with the 9948 rev. (Though I have experienced the
same bug with revisions of May).
Currently I am taking a checkpoint inside a benchmark and restore it with Ruby
+ OoO CPU.
If I do it with the simple network model or garnet flexible it works fine.
H
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