can freely use/modify this simulation platform as long as you follow
gem5's copyright rules, and please don't forget to cite our paper.
Thank you,
Best Regards,
--
Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEI - University of Bologna, Italy
https://www.linkedin.c
n someone please give me some details on how to do that?
>
> If not can someone confirm that?
>
> Thanks,
> Doru Thom Popovici
>
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on? If so, how?
>
> Thanks in advance,
>
> Regards,
> Sarah
>
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--
Erfan Azarkhish
Micrel Lab - Viale Carl
PhD Candidate in Electronic and Computer Systems
>
> School of ICT
> KTH Royal Institute of Technology
>
> yuan...@kth.se
>
>
>
>
>
>
>
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> http://m5sim.org/c
f patches on RB that I’m about to push that also makes uncacheable
> accesses snoop into the caches properly.
>
> I hope that provides some clarity.
>
> Regarding your kernel panic I’d say the best way forward is to start
> digging in and debug what is happening.
>
> Andre
cr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
Can anybody help me with this issue?
Thanks in advance,
Best Regards,
--
Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEI - University of Bologna, Italy
ht
, 2015 at 6:53 PM, giorgos k via gem5-users <
gem5-users@gem5.org> wrote:
>
>
> Erfan Azarkhish via gem5-users gem5.org> writes:
>
> >
> >
> >
> > Dear Girogos,
> >
> > If you modify DramCtrl.py, you will have to rebuild gem5, otherwise t
t; totally 4 ranks.The system has 1024MB of ram. Is it right when i change the
> rank per channel from 2 to 1 and the number of channel from 2 to 4 on the
> second architecture on the DramCtrl.py file or do i have to do something
> else in order to compare the two architectures??
>
>
-- Forwarded message --
From: "Erfan Azarkhish"
Date: Oct 29, 2014 10:15 AM
Subject: Re: [gem5-users] Seg Fault with Multi-channel Memory
To: "Patrick L." , "gem5 users"
Cc:
Hi Patrik,
Are you using gem5-stable? Because support for multichannel mem
freeable+0x1b8/0x1d8
[2.542584] [] kernel_init+0x10/0xd4
Could someone please help me?
Thanks a lot
Best,
--
Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEI - University of Bologna, Italy
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name of my library to the compiler.
Thanks,
--
Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEI - University of Bologna, Italy
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(from the main
processors), also Write/Read to main memory from inside this accelerator.
Thanks in advance,
--
Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEI - University of Bologna, Italy
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gem5-users
support atomic accesses?
> If this is correct, is there any workaround for this? I need to use fast
> forwarding in my simulations.
> Please throw some light on this.
>
>
> On Thu, Jun 27, 2013 at 10:10 AM, Erfan Azarkhish
> wrote:
>
>> Hi,
>>
>> Can yo
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Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEIS - University of Bologna, Italy
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n,
>
> Today you cannot connect two buses directly to each other. You will need
> to either insert a cache or bridge in between.
>
> The error you see seems to suggest you have connected two ports on the
> buses to each other (which is causing the multiple-range issue).
>
>
system.
membus2.slave[0]
I
want to make a complex topology and I need to connect the buses to each
other
T
hanks
--
Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEIS - University of Bologna, Italy
___
gem5-users mailing
y suggesting a good starting point or direct me to
> one?
>
> Thanks in advance!
> Sanjay.
>
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Erfan Azarkhish
M
Hi,
Can somebody please tell me about the purpose of system_port in python
configurations? What does it do? Is it possible to connect it to more than
one bus?
self.system_port = self.membus.slave
Thanks a lot
--
Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEIS
, Ali Saidi wrote:
> It looks like you don't have libssl installed.
>
> Ali
>
>
>
> On Jun 10, 2013, at 7:48 AM, Erfan Azarkhish
> wrote:
>
> Dear All,
>
> I have been using gem5 on Ubuntu 11.10 without any problems. However,
> recently I reinstalled my
ndefined reference to
`EVP_MD_CTX_copy@OPENSSL_1.0.0'
/usr/lib/libpython2.7.so: undefined reference to
`CRYPTO_num_locks@OPENSSL_1.0.0'
/usr/lib/libpython2.7.so: undefined reference to
`SSL_CTX_get_verify_mode@OPENSSL_1.0.0'
...
C
an you please help me with this issue
Sincerely,
--
Hi,
I had exactly the same problem, and since some benchmarks take a really
long time with detailed ruby networks, I have to stop them before the
end, so sometimes I have 2 dumps and sometimes 1
So, how do I understand which of the stats contains useful information
for me? I just look at the C
Dear All,
I wanted to checkpoint from a full system simulation of 4 Alpha processors
connected to a Ruby crossbar. I faced this error:
panic: Runtime Error at MI_example-cache.sm:122, Ruby Time: 27920363907,
Invalid RubyRequestType.
C
an anybody help me with it?
Thanks
--
Erfan Azarkhish
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