Yes, but you need to use the magic address call mechanism, not the default
special instruction mechanism which KVM doesn't recognize since it's
executing on real hardware. If you're calling from userspace, then you can
use the map_m5_mem() function to mmap /dev/mem so you can access the right
physi
however I haven’t looked into the error
> carefully yet, it may just because for some reason the lib is still trying
> to use the magic instruction interface. But before I proceed any further,
> just want to make sure I was using the correct approach to do this.
>
> Best,
> Wenq
Hi Ciro. You are correct that there isn't a header for those symbols,
although the signature for m5_exit and m5_exit_addr should be identical.
The mechanism supporting those symbols should all be in place and there are
unit tests for them, although those tests are at least partially still
under rev
The IRET instruction is implemented in
arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py.
It's fairly involved since IRET is an inherently complicated instruction,
but it's commented and follows the pseudo code which was in the AMD manuals
at the time it was written.
I think the confusion comes from the fact that accesses in atomic mode
return right away, where in timing mode they are split into a call which
starts the transaction, and a callback with the results. In atomic mode,
the same function can loop through all the lookups that might be necessary
since t
Hi Wenqi. The updated libm5.a should be used in basically the same way as
the old version. Just link against the library, include the header file,
and call into the op you want using the normal function call syntax.
Hoa, the documentation you've linked to is a little out of date. How can it
be upd
The VirtIO device would be a pretty good example, although it does some
unusual things as far as determining how big it's BARs are supposed to be.
The IDE controller is a pretty simple device that's a little more
representative in that way. A lot of the complexity is in the actual disks
themselves,
As far as I know those patches should no longer be necessary, although I
haven't tried to run KVM on x86 recently. Other problems could be that KVM
isn't enabled in your BIOS or your operating system, or that the
permissions on the device file gem5 needs to start a VM isn't set properly.
Unfortunat
It looks like your libpython3.8.a was not built with the same compiler as
the one you're trying to build gem5 with. Extra information it sets aside
for LTO (link time optimization) is apparently not compatible between the
two versions.
Gabe
On Thu, Oct 15, 2020 at 5:14 PM Shivakumar,Raghul via ge
I think you mean the TimingSimpleCPU, not the AtomicTimingCPU.
Gabe
On Thu, Oct 15, 2020 at 1:41 PM Bobby Bruce via gem5-users <
gem5-users@gem5.org> wrote:
> Hey Krishnan,
>
> Linux does take about 45 minutes or so to run using AtomicSimpleCPU.
> You're not doing anything wrong in this regard.
Those are not errors, or at least not errors that will prevent the build
from being successful. The linker errors (DWARF error: ...) are unfortunate
but don't prevent the build from finishing. I don't know what, if anything,
might be affected by them. The other message is just a warning.
Gabe
On
Hi Liyichao, you can register a callback with the
Stats::registerResetCallback function in base/statistics.hh.
Gabe
On Mon, Oct 12, 2020 at 7:15 PM Liyichao via gem5-users
wrote:
> Hi All:
>
>
>
>
>
>When I use gem5 + O3 based on armv8 with NVMAIN ddr4 model, I want
> to know *how I can
To see how to integrate with gem5's systemc kernel, look at the examples
in util/systemc/systemc_within_gem5/ (not a great place for examples, I
know). To use TLM, you can take a look at the TLM/gem5 bridge
in src/systemc/tlm_bridge/. That's not intended as an example, but it's
relatively simple an
Please speak to other members of our community with respect. Nobody owes
you help, and nobody is likely to volunteer it to someone with a bad
attitude. Don't send emails to both gem5-users and gem5-dev, gem5-users is
enough.
Gabe
On Thu, Oct 1, 2020 at 6:42 PM 1154063264--- via gem5-users <
gem5-
PTAL
https://gem5-review.googlesource.com/c/public/gem5/+/33695
https://gem5.atlassian.net/browse/GEM5-753
Gabe
On Thu, Aug 27, 2020 at 4:24 AM Daniel Carvalho via gem5-dev <
gem5-...@gem5.org> wrote:
> Hello,
>
>
> This message only concerns those who use the *develop* branch.
>
>
> We have re
You shouldn't modify your config by changing anything in src/, you should
do that in the config scripts. If you want to add additional devices, they
don't have to be part of the platform object, they just need to be
connected to the right busses, etc.
Gabe
On Fri, Aug 28, 2020 at 12:06 PM HENG ZH
Do you have enough in the partition/disk/etc you're building gem5 in? If
you have lots of disk space but it's assigned some other purpose, you can
still run out. This pretty clearly looks like you're running out of disk
space to me.
Gabe
On Fri, Aug 28, 2020 at 12:43 PM Dwaipayan Ray via gem5-use
Generally speaking, gem5 tends to be pretty loose as far as checking
whether instructions are privileged or not. Real programs tend to behave
themselves because on a real system they would crash if they didn't. That
means it's usually not very important to implement those checks to get
correct (or
I don't think so, although I don't know that for certain. Bobby? Andreas?
Gabe
On Mon, Aug 24, 2020 at 8:47 PM mike upton via gem5-users <
gem5-users@gem5.org> wrote:
>
> Is there a defined regression for KVM cpu tests?
> For both X86 and ARM.
>
>
> __
You have to set the kvm_vm parameter of the System object.
Gabe
On Sun, Jul 26, 2020 at 10:57 PM Soramichi Akiyama via gem5-users <
gem5-users@gem5.org> wrote:
> Hi,
>
> I am trying to fast-forward a large workload with X86KvmCPU, but the
> constructor falls into a segmentation fault.
> I use th
You can use your own debug flags in FS mode. The stats should mostly be
deterministic, particularly in FS mode, but if the simulation interacts
with something else that's not deterministic, like if you type on its
console or it runs system calls on the host in SE mode, then things can
change from r
A long time ago when gem5 just supported Alpha, there were three types of
registers, integers, floats, and everything else. The "everything else"
were essentially control registers, or in other words registers which had
side effects from accessing them. They were called "Misc" for miscellaneous
sin
You haven't specified a kernel. gem5 doesn't (typically) look on the disk
image for the kernel, you need to pass that in separately.
Gabe
On Tue, Jun 23, 2020 at 7:32 AM Saeed Seyedfaraji via gem5-users <
gem5-users@gem5.org> wrote:
> Dear Users I have a problem with X86 full system simulation.
Conceptually yes. There is usually an event or something an event causes
which tells gem5 to exit, like the last thread of a process exiting, or the
m5 utility running inside a full system simulation telling the simulator it
wants to exit. That will make gem5 return to the config script where it
wi
Events are scheduled for a specific time, and it's the event queues job to
go through them in chronological order and call them to do whatever they're
supposed to do. Events happen instantly, in the sense that time does not
pass or change while they're running. They also can't normally affect what
SimObject is a special case and is imported from "SimObject". MemObject
(and all other SimObject subclasses) are imported from m5.objects.*. You're
import should be from m5.objects.MemObject import MemObject.
Gabe
On Mon, Jun 15, 2020 at 5:34 AM Shaikhul Hadi via gem5-users <
gem5-users@gem5.org>
Actually, could you file a bug for this over on Jira?
https://gem5.atlassian.net/secure/BrowseProjects.jspa
I'm not sure what limits it has on file size, etc., but that might be a
good place to upload the binary you're trying to run.
Gabe
On Wed, Jun 10, 2020 at 8:41 PM Gabe Black wrote:
> cc
I filed a bug for this on Jira:
https://gem5.atlassian.net/browse/GEM5-629
On Wed, Jun 10, 2020 at 5:44 PM Gabe Black wrote:
> ==5823== 1268 errors in context 4 of 62:
>> ==5823== Conditional jump or move depends on uninitialised value(s)
>> ==5823==at 0x886949: MemState::fixupFault(unsigne
cc-ing a couple AMD folks in case they have some input or want to know that
there's a potential bug here.
Ignoring the last error which I addressed in a different email, this looks
like some sort of (gem5) stack corruption. Note that this doesn't directly
have anything to do with the stack in the
>
> ==5823== 1268 errors in context 4 of 62:
> ==5823== Conditional jump or move depends on uninitialised value(s)
> ==5823==at 0x886949: MemState::fixupFault(unsigned long)
> (mem_state.cc:426)
> ==5823==by 0xB7DB3C:
> X86ISA::TLB::translateFunctional(std::shared_ptr const&,
> ThreadContex
SSE2 should work with no problems. It's very unlikely this has anything to
do with the compiler you're using for your benchmark, other than that it
might coincidentally set up a scenario which exposes a bug. If your program
has a bad instruction in it somehow, the decoder should handle that just
fi
The files in that tar are all for Alpha, and you're trying to use them on
an X86 version of gem5 (which simulates x86). Since Alpha support has been
removed, we should also delete that tar ball and any reference to it from
the website. Where did you see instructions to download it?
Gabe
On Mon, M
Hi, I see two problems with your implementation. First, where you call PIM
in pseudo_inst.cc, you don't actually do anything with the result so it's
just dropped. Second, in two_byte_opcodes.isa, you don't do anything with
the result of PseudoInst::PIM. You need to put the result in RAX for it to
b
Whoops, now I did it :-). I meant build/ARM/gem5.opt.
Gabe
On Sun, Apr 26, 2020 at 4:20 AM Gabe Black wrote:
> Hi, I noticed that you're trying to run an ARM kernel on gem5 compiled to
> run x86 code. That won't work. You need to either use an x86 kernel, or the
> ARM version of gem5, aka build
Hi, I noticed that you're trying to run an ARM kernel on gem5 compiled to
run x86 code. That won't work. You need to either use an x86 kernel, or the
ARM version of gem5, aka build/X86/gem5.opt.
Gabe
On Sat, Apr 25, 2020 at 10:50 PM Taiyu Zhou via gem5-users <
gem5-users@gem5.org> wrote:
> Hi Ci
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