[gem5-users] Re: Using Garnet without cache coherence model

Hi Olumide, The "Garnet standalone" protocol is meant to be used when you want to use garnet without a coherence protocol. Hopefully that works for your use case. Cheers, Jason On Mon, Nov 4, 2024 at 9:55 AM Olumide via gem5-users wrote: > Hello gem5-users, > > Is it possible to use Garnet to

[gem5-users] Re: Simulation determinism

Hi Hossam, When using the KVM CPU you won't get deterministic results. Since the KVM CPU is using your *host* processor to execute the instructions (1) there is no determinism across hosts and (2) there's no API to get instruction-perfect simulation intervals. If you use the atomic CPU for fast-f

[gem5-users] Re: [EXT] Re: Does GarnetPt2Pt and GarnetMesh still work in Gem5?

Replacement policies should be fully supported. On Mon, Oct 28, 2024, 8:44 AM Beser, Nicholas D. wrote: > Jason, > > > > There was a comment in the charts that the replacement policy was broken. > Is that still the case? > > > > I wanted to assign the students a task to experiment with different

[gem5-users] Re: Does GarnetPt2Pt and GarnetMesh still work in Gem5?

Hi Nick, The generic topologies in Ruby (e.g., the ones in configs/topologies) were always *very brittle*. This was especially so for topologies like Mesh where the topology is tightly coupled to the number of each type of controller (and even the coherence protocol!). Therefore, in the stdlib we

[gem5-users] Re: question about bootcamp 2024 slides on Cache Hierarchies

Hi Nick, On Sat, Oct 12, 2024 at 4:42 PM Beser, Nicholas D. via gem5-users < gem5-users@gem5.org> wrote: > Jason, > > > > I went through both the youtube and slides for the talk on > cache-hierarchies. I have some question that I hoping you might answer. The > ruby example in the slides looked at

[gem5-users] Re: Problems with example from bootcamp 2024

Hi Nick, I think there's another typo: "My_MSI.slicc" != "MyMSI.slicc" Apologies if the bootcamp documentation is inconsistent. If you see inconsistencies in the upstream bootcamp, it would be great to open an issue on that repo. Cheers, Jason On Tue, Oct 8, 2024 at 6:19 AM Beser, Nicholas D. v

[gem5-users] Re: Problems running ruby example from bootcamp 2024

Hi Nick, It looks like I need to add a slide to that deck :). You need to add/modify a Kconfig file like this one: https://github.com/gem5/gem5/blob/stable/src/learning_gem5/part3/Kconfig Cheers, Jason On Sat, Sep 21, 2024 at 6:45 PM Beser, Nicholas D. via gem5-users < gem5-users@gem5.org> wrot

[gem5-users] Re: Problems running mips with gem5

Hi Nick, I have no idea, to be honest. We don't ever test MIPS. I would dig into the code to figure out if this was ever an option. When we pushed changes to the build system to use Kconfig it's possible that we accidentally removed this build option. Cheers, Jason On Sun, Sep 15, 2024 at 1:10 P

[gem5-users] Re: Error message when compiling for ARM (Jetson orin nano)

That's almost certainly that you're running out of memory. Try using fewer cores (smaller -j). Cheers, Jason On Mon, Sep 16, 2024 at 7:59 AM Beser, Nicholas D. via gem5-users < gem5-users@gem5.org> wrote: > I attempted to compile gem5.opt (ALL) and received the following error > message: (After

[gem5-users] Re: What models are included with generic build/ALL?

Hi Nick, All CPU models are included in all builds except when no ISAs are selected (NULL). When building gem5 with support for more than 1 ISA instead of using just "O3CPU" you have to use an ISA-specific version (e.g., ArmO3CPU). The standard library will hide some of the details from you if you

[gem5-users] Re: [EXT] Re: Building Bootcamp 2024

Oh, we don't have an Arm image for this container (right now). Apologies for the confusion. Maybe that version of gcc isn't available for Arm? Any GCC > 9 should work, IIRC. Cheers, Jason On Fri, Aug 9, 2024 at 11:27 AM Beser, Nicholas D. wrote: > Jason, > > > > I don’t think I ran out of disk

[gem5-users] Re: Building Bootcamp 2024

Hi Nick, I don't know why this is failing. Maybe you ran out of disk space? You can use a prebuilt version of the devcontainer from ghcr.io/gem5/devcontainer:bootcamp-2024. See https://github.com/orgs/gem5/packages/container/package/devcontainer Cheers, Jason On Thu, Aug 8, 2024 at 3:50 PM Bese

[gem5-users] Re: how to integrate garnet with the classic memory system

Hi Chitanda, You cannot use garnet with classic memory system. You can only use garnet with Ruby. Thanks, Jason On Tue, Jun 11, 2024 at 11:35 PM 841857649 via gem5-users < gem5-users@gem5.org> wrote: > Hi, > > > I’m trying to modify networkinterface.cc, network.cc and some other files > but

[gem5-users] Re: Difference between using the Configuration Script vs Standard Library?

Hi Kaze, Thank you for reaching out and expressing your interest in gem5 simulations. I understand that you’re curious about the difference between the configuration script and the standard library when executing the SE binary with the same parameters. gem5’s interface is primarily based on Pytho

[gem5-users] Re: catching the traces of communication between the processors

Note: this is the output from the gem5 GPT ( https://chat.openai.com/g/g-o3y1y4t8J-gem5-gpt/) Certainly, Ojas! To capture traces of communication between processors in your gem5 simulation, a more specialized approach involves using the Communication Monitor component. This feature is designed to

[gem5-users] Re: Limit debug output to certain instruction address range

Hi Hossam, If you're using the stdlib, you can override the default ROI begin handler. See the documentation here: https://github.com/gem5/gem5/blob/stable/src/python/gem5/simulate/simulator.py#L145 If you're not using the stdlib, then look for where the code you're using calls m5.stats.dump() an

[gem5-users] Re: Can I use RiscvO3CPU with TSO?

Hello, That *should* work, but my confidence isn't very high. I suggest running tests to see if you can produce TSO and non-TSO executions with and without the option. Cheers, Jason On Thu, Feb 15, 2024 at 12:32 PM Z HW via gem5-users wrote: > > I know that RISC-V assumes RVWMO. But if I want

[gem5-users] Re: Executing Binary Code in FS without a Kernel

Hi Alain, I'm the gem5-GPT bot, here to assist with your queries about the gem5 simulator. Please note that while I aim to provide accurate information, my responses could be wrong or may have been slightly edited for clarity. You can access the gem5-GPT on chat.openai.com/g/g-o3y1y4t8J-gem5-gpt i

[gem5-users] Re: Limit debug output to certain instruction address range

Hi Hossam, > Yet another option is a way to enable/disable debugging in the config script mid-simulation. This would allow me to exit the simulation using an m5op before the instructions, enable debugging in the config script, continue, exit using an m5op after the instructions, disable debugging

[gem5-users] Re: How to suspend FS simulation after certain number of ticks

Hello, Unfortunately, we don't have enough time to answer all questions in depth. You may be able to find more help on either the gem5 slack or the gem5 youtube channel . If you have access to ChatGPT Plus, you can also use the gem5

[gem5-users] Re: Can CloudSuite Run on FullSystem Simulation

Hello, Note: the output below is from the gem5-GPT. If you have chatGPT Plus you can access this GPT/bot at https://chat.openai.com/g/g-o3y1y4t8J-gem5-gpt. I've made some inline comments as well. Hello! Regarding your queries about running CloudSuite on gem5 in Full System (FS) mode with x86 ISA

[gem5-users] Re: Adding 9p support to the riscv-fs platform not working

Hi Thilo, My guess is that you need to add a node to the device tree. I would look at the device tree generated for Arm and see if you can pattern match what you need to add for RISC-V. Cheers, Jason On Mon, Oct 2, 2023 at 1:12 AM Thilo Voertler via gem5-users < gem5-users@gem5.org> wrote: > Hi

[gem5-users] Re: Sharing cache lines at memory level

Hi Arteen, This is dependent on the Ruby coherence protocol you are using. It sounds like you're using MESI_Three_Level or MESI_Two_Level in which the LLC is a single logical cache that is banked between different instances. If you want something more like "cluster-private" LLC slices, then you'll

[gem5-users] Re: Libthreads for Gem5

Hi George, You can use pthreads. There's no need for m5threads anymore. The only wrinkle is that you have to make sure the cross-compiled dynamic libraries are in the right place. You can use the "redirect paths" option to map a path on the host to a different location in the guest (like volumes i

[gem5-users] Re: Generate Multiple Trace Files for Multi-Threaded Workloads on FS

Hi Abdelrahman, Thank you for your questions on the mailing list. I will try to answer them as best as I can. - The trace CPU model was not designed to support multithreaded applications or multiple cores. It was only tested with single-threaded benchmarks in both SE and FS mode. Therefore, gener

[gem5-users] Re: can't run riscv simulation with any CPU model except Atomic

Hello, These scripts are tested nightly, so they should be working. How long did you wait for the terminal output? It can take 15-30 minutes before you see any output. Cheers, Jason On Wed, Aug 23, 2023 at 5:00 AM oe-fans via gem5-users wrote: > hi, all > > I built gem5 v23.0.1.0, I can run co

[gem5-users] Re: Memory allocation when using heterogeneous memory controllers

Hi Jaeyong, No, there's no way to distinguish the memory types in SE mode. You will have to modify the memory allocator or use `Process.map` ( https://github.com/gem5/gem5/blob/develop/src/sim/Process.py#L39) to map specific virtual addresses to physical addresses. If you use `map` you can then us

[gem5-users] Re: How to solve "AttributeError: Can't resolve proxy" error when l1icache is replaced with new module

Hi Shaikhul, I think that you have somehow unset the `assoc` parameter (or set it to None) in the cache. Can you provide us the exact script you're running, the command line that you use to run, the information about the gem5 build (variant used), the version of gem5 you're using, and any modifica

[gem5-users] Re: Prefetching during instruction decode

Hi Pedro, On quick suggestion: It may make sense to put the prefetcher in the CPU model code (e.g., during the decode stage in the O3CPU) instead of in the decode logic of the ISA. After you get the `StaticInst` from the decoder, you should be able to push prefetch requests into the instruction ca

[gem5-users] Re: RISCV Vector Extension in gem5

Hello, No, we don't have any explicit documentation on this. I think that the fault-only-first are the few instructions that are not implemented. Cheers, Jason On Thu, Aug 3, 2023 at 10:25 PM X BJ wrote: > Hello, > > Thank you very much, it is exactly what I need ! > > BTW, is there a instruct

[gem5-users] Re: RISCV Vector Extension in gem5

Hello, Initial RVV support was just merged today! See https://github.com/gem5/gem5/pull/83 On Thu, Aug 3, 2023 at 12:29 AM 谢 佰杰 via gem5-users wrote: > Hi all, > I found that both rivosInc and RALC888 used to work on RISC-V Vector > Extension in gem5, but both of them seem to be busy with othe

[gem5-users] Re: ARM KVM Switch + Restoration

This should work... can you provide an example script and specific commands to reproduce the error? Thanks, Jason On Tue, Aug 1, 2023 at 11:24 AM AbdelQader AlKilany via gem5-users < gem5-users@gem5.org> wrote: > Hello gem5 users, > > > > I was wondering if it is possible to start a FS ARM simul

[gem5-users] Re: Unable to boot Linux in FS mode

Hi Zhenwen, The actual error is one line higher in the kernel output: `/lib/x86_64-linux-gnu/libc.so.6: CPU ISA level is lower than required` I believe we fixed the incompatibility of gem5-x86 with newer kernels in gem5-v22.1, but it is definitely fixed in gem5-v23.0. I suggest either updating ge

[gem5-users] Re: Using Traffic Generators with Ruby

Hi Vishnu, I do not believe there is any way to direct traffic to a particular message buffer (e.g, `requestToDir`). Ruby is in some sense a "black box" that only has port inputs (which are directed to a sequencer) and port output (via `requestToMemory`). That said, this is a cool idea! I would e

[gem5-users] Re: stopping simulation via ThreadContext::halt()

Hi David, I think you want to call the function `exitSimLoopNow` or `exitSimLoop`. You can call this function from an instruction implementation, (e.g., halt), I believe. See https://github.com/search?q=repo%3Agem5%2Fgem5+exitSimLoop+&type=code Cheers, Jason On Wed, Jul 26, 2023 at 9:39 AM Davi

[gem5-users] Re: Facing issue while trying to use PARSEC benchmark using Gem5

Hi Abhinav, I would suggest using the most recent version of gem5 (v23.0) and use the gem5-resources version of parsec. See https://resources.gem5.org/resources/x86-parsec/example?database=gem5-resources&version=1.0.0 for an example using parsec. Cheers, Jason On Thu, Jul 27, 2023 at 2:14 AM Abh

[gem5-users] Re: Inquiry about using RiscvTimingSimpleCPU to connect with TLM memory in Gem5

Hi Zitai, You should be able to use any CPU model with the TLM interface. You can write your own configuration file / run script that creates a TimingSimpleCPU and connects the I/D ports to the TLM interface. Cheers, Jason On Thu, Jul 27, 2023 at 2:44 AM 泰。 via gem5-users wrote: > Hi： > > I am

[gem5-users] Re: potential error in gem5 simulation?

There's a lot of information missing in your email, but I'll make some guesses and try to help. If you're using x86 and you compiled lbm on your host, then most likely it is using SSE/AVX/vector instructions that may not be implemented or implemented incorrectly in gem5. I would expect to see warn

[gem5-users] Re: Question about pulling in the latest version of gem5 with the bootcamp 2022 files.

Hi Nick, You should be able to `cd` to the gem5 directory, set up a remote to the new github location (`git remote add upstream https://github.com/gem5/gem5`) then checkout stable (`git checkout upstream/stable`). (Note: commands off the top of my head and may have mistakes.) That said, be carefu

[gem5-users] Re: Meltdown simulation & analysis in FS mode using fs.py

Hi Robin, This may be helpful: http://www.lowepower.com/jason/visualizing-spectre-with-gem5.html For `warn: instruction 'palignr_Vdq_Wdq_Ib' unimplemented`, this is an AVX (or SSE) instruction that gem5 doesn't implement. Overall, I'm not sure if gem5 is vulnerable to meltdown. I think that the

[gem5-users] Re: Adding a delay of certain ticks in gem5

Hi John, The following may be helpful: https://gem5bootcamp.github.io/gem5-bootcamp-env/modules/developing%20gem5%20models/events/ https://www.youtube.com/watch?v=OcXA1D4b1RA&t=3868s Cheers, Jason On Thu, Jul 6, 2023 at 9:53 AM Eliot Moss via gem5-users < gem5-users@gem5.org> wrote: > On 7/6/2

[gem5-users] Re: Hi does gem5 Ruby support pthreads lock and unlock

Full system mode is fully supported for RISC-V. There should not be any problems with running pthreads on RISC-V. (Side note: There could be a small bug in the RISC-V atomic instructions... we're looking into it, but haven't been able to track it down.) Cheers, Jason On Thu, Jun 29, 2023 at 4:05

[gem5-users] Re: simulate a multi-core processor with Gem5

Hello, You may also find the "Learning gem5" documentation https://www.gem5.org/documentation/learning_gem5/introduction/ and the bootcamp videos https://www.youtube.com/playlist?list=PL_hVbFs_loVSaSDPr1RJXP5RRFWjBMqq3 useful. Cheers, Jason On Tue, Jun 20, 2023 at 10:49 AM Eliot Moss via gem5-us

[gem5-users] Re: About Risc-V custom ISA

Hello, I believe you would have to modify your compiler to emit the instruction to avoid using embedded assembly. Cheers, Jason On Tue, Jun 20, 2023 at 10:36 AM 中国石油大学张天 via gem5-users < gem5-users@gem5.org> wrote: > When I have customized a RISC-V instruction, I want to know how to make > the

[gem5-users] Re: Writing a script to run multiple simulations at once

Hi all, You can use python multiprocessing with gem5. See https://github.com/gem5/gem5/tree/develop/src/python/gem5/utils/multiprocessing for details. So, in theory, you can create scripts such that you can run `./gem5 run.py` which will run a set of different experiments. You could potentially e

[gem5-users] Re: [EXT] Re: Question about running the hpca-2023 tutorial

Hi Nick, I think you have a typo. It's `gcr.io` as in "google *c*ontainer registry." I believe you have an "e" instead of a "c" in your URL. Cheers, Jason On Sat, Jun 10, 2023 at 7:52 AM Beser, Nicholas D. via gem5-users < gem5-users@gem5.org> wrote: > Bobby, > > > > I tried your recommendation

[gem5-users] Re: [EXT] Re: Question about running the hpca-2023 tutorial

Hi Nick, For teaching you may be able to get some inspiration from my class assignments. Specifically, assignment 5 is about coherence: https://jlpteaching.github.io/comparch/modules/gem5/assignment5/ All of the code for my assignments can be found here under different branches for each assignmen

[gem5-users] Re: Multi-level TLB is implemented in performance

Thanks > Arun > > On Wed, Oct 28, 2020 at 9:01 PM Jason Lowe-Power via gem5-users < > gem5-users@gem5.org> wrote: > >> Yes, this is possible, and I believe it's already implemented for Arm. >> >> The best place to start is src/arch//tlb.cc >> >>

[gem5-users] Re: Full System + external memory

Hi Jonathan, You can put the bridge wherever you would like. For MMIO things, you can put it after the point of coherence, which is where we usually put the "I/O crossbar." You can poke around in configs/examples and util/systemc for some examples. Cheers, Jason On Wed, Apr 26, 2023 at 4:30 PM

[gem5-users] Re: Full System + external memory

Hi Jonathan, Absolutely! You can set up a "bridge" which will take a subset of addresses and route to a different gem5 port. If you can convert from the port interface to the AXI, then it should "just work". Note that there are also already bindings to SystemC/TLM in gem5 as well that could serve

[gem5-users] Re: I really want these files for old x86 gem5

Hi Xiang, I would advise against using such old resources for current research. Using an OS from a decade ago may not give you results that are accurate for today's systems. For "linux-bigswap2.img", this is just an empty disk image that was used as swap space. You can probably use an empty file

[gem5-users] Re: Question Regarding L1 Cache Transient States handling Load Hit in Ruby MOESI CMP Directory protocol

Hello, This is a great question! The short answer is I believe that the coherence protocol is correct. (Though, there could always be unexpected bugs.) The slightly longer answer: You are probably seeing that the store happens before the load in "real" time. However, in the processors' view (i.e

[gem5-users] Re: Capturing SimPoint and running on ARM CycleModel

Yes, that's correct. Cheers, Jason On Thu, Mar 9, 2023 at 9:44 AM Jonathan Kang wrote: > I think I’d want the opposite: to get ELFies out of Gem5 CheckPoints. > That’ll allow me to run it on an ARM Cycle Model. > > > > From the links you sent, it’s still Pin based and the resulting ELFies are >

[gem5-users] Re: Capturing SimPoint and running on ARM CycleModel

Hi Jonathan, We just did a tutorial on how to use ELFies with gem5. See https://looppoint.github.io/hpca2023/ for details. We are able to load ELFies and run them in gem5. See https://github.com/gem5-hpca-2023/gem5-tutorial-codespace/blob/master/elfie-refs/elfie.py for an example. That said, we

[gem5-users] Re: Location of gem5 dist

Hi Rajesh, You can find all of the links in this json file: https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/resources.json It's not very user-friendly, but we're working on it :) Cheers, Jason On Fri, Feb 17, 2023 at 10:15 AM Rajesh Shashi Kumar via gem5-users < gem5-use

[gem5-users] Re: Query about Support for Chiplet Architecture

Hi Zhengrong, On Thu, Jan 12, 2023 at 2:40 PM Zhengrong Wang via gem5-users < gem5-users@gem5.org> wrote: > Hi All, > > Our group has been using gem5 for architecture research for a long time, > and we currently want to explore some ideas on modern multi-chiplet > architectures, e.g. AMD's EPYC.

[gem5-users] Re: DerivO3CPU panic: initiateAcc not defined: ROB fills and locks up

Hi Eliot, Unfortunately, I don't have a direct answer for you. However, I want to say that I appreciate you keeping the mailing list updated with your progress! Cheers, Jason On Fri, Jan 6, 2023 at 10:07 AM Eliot Moss via gem5-users < gem5-users@gem5.org> wrote: > On 1/4/2023 11:51 PM, Eliot Mo

[gem5-users] Re: Command line options to modify the replacement policy in gem5

Hi Vipin, The interface to gem5 isn't the command line, it's a python runscript. In your python script, you can add parameters (e.g., with optparse) which are accessible from the command line, but this shouldn't be considered the main interface to modifying the parameters of gem5 objects. If you w

[gem5-users] Re: Panic when running gem5 Full System mode

I believe the problem is with the kernel binary you are passing in. It needs to be the path to the binary (not a directory), and it must be the uncompressed kernel binary, not the compressed binary. Cheers, Jason On Tue, Nov 22, 2022 at 11:06 AM JASPINDER KAUR via gem5-users < gem5-users@gem5.org

[gem5-users] Re: SPEC CPU 2017 taking days to simulate

mpoint with gem5 v22? Thanks a lot! > > > > BR, Markus > > > > On 08.11.2022, at 20:10, Jonathan Kang wrote: > > > > Something as big as Spec typically wouldn’t be simulated as a whole but > rather, using SimPoint on a cycle-accurate model. > > > >

[gem5-users] Re: SPEC CPU 2017 taking days to simulate

PM yaogang wrote: > Hi Jason, > > > >Is there any roadmap (near future not long term) to take gem5 to multi > thread accerleration? > > > > Regards > > Yao > > > > *发件人:* Jason Lowe-Power via gem5-users [mailto:gem5-users@gem5.org] > *发送时间:

[gem5-users] Re: SPEC CPU 2017 taking days to simulate

Hi Markus, I would expect gem5 to be at least 10,000-100,000x slower than your host. So, if it takes 100 seconds on the host, then I would expect between 1,000,000 and 10,000,000 seconds or more! That's 277-2770 hours or 10-100 days!! BTW, I actually think a 10-100,000x slowdown is on the low si

[gem5-users] Re: Low memory bandwidth achieved with STREAM benchmark

Majid, These are all great suggestions! Do you have a configuration file that you would be willing to share? It would be a huge benefit to the community if we had some better default configurations in the "examples" for gem5 configuration files. We're also trying to use the new standard library f

[gem5-users] Re: Adding PioDevice leads to TypeError: No constructor defined

I just pushed a change that will make this error message better. "fatal: Cannot instantiate an abstract SimObject (system.dev)" is what the error now says :). See https://gem5-review.googlesource.com/c/public/gem5/+/59049 Cheers, Jason On Fri, Apr 22, 2022 at 8:57 AM Jason Lowe-Power wrote: >

[gem5-users] Re: Adding PioDevice leads to TypeError: No constructor defined

Hello, I believe the problem is that gem5 tries to do too much automatically for you! gem5 automatically creates a lot of the constructor/destructor codes. Given all of this hidden/automatic code generation, it's difficult to know exactly what's going wrong (for both you and for us). That said, I

[gem5-users] Re: Integrating MCPAT with gem5

Hi Vipin, McPAT is not the same kind of simulator as SST, DRAMSim, and SystemC, so it cannot be integrated in the same way. It's not really a timing simulator at all. You can use gem5's statistics output as the "activity rate" which is one of the inputs to McPAT. However, the other inputs (e.g., t

[gem5-users] Re: How to set the Cache replacement policy

Hi Ankit, I would suggest modifying your python runscript instead of using command line parameters. https://www.gem5.org/documentation/learning_gem5/introduction/ may help explain how to set parameters on SimObjects. Cheers, Jason On Wed, Apr 6, 2022 at 2:48 PM Ankit Berde wrote: > Hi Gem5 Tea

[gem5-users] Re: How does an out of order pipeline implementation handle instructions (cmp, adds,cmn etc.) which update N,Z,C,V?

Hi Tom, On Tue, Mar 29, 2022 at 9:39 AM tomjosekallooran--- via gem5-users < gem5-users@gem5.org> wrote: > Hi , > This may sound very generic, but i want to try some experiments with the > out of order implementation. I came across few scenarios, which are listed > below (any input would be helpf

[gem5-users] Re: Problem with SimObject

Hi Artyom, You're absolutely right that the tutorial needs to be updated! The website is also open source and managed via a git repo: https://gem5.googlesource.com/public/gem5-website/. Updating this would be a good way to get started contributing to gem5 :). By the way, for the namespace, you ca

[gem5-users] Re: gem5 and non volatile memory

Hello Taiyu, I would suggest reaching out to the VANS authors. Since this project is not part of the gem5 repository, we have little control over the integration. Cheers, Jason On Thu, Mar 24, 2022 at 8:49 PM Taiyu Zhou via gem5-users < gem5-users@gem5.org> wrote: > Could you give me some advis

[gem5-users] Re: CXL protocol/model implementation

Hi Zicong, 1. I personally don't believe that CXL in SE mode would be very interesting. From my point of view, CXL would be interesting only to capture the OS and system-level effects. That said, you may be able to test CXL.cache in SE mode. 2. To implement the different protocols: CXL.io: This

[gem5-users] Re: Issue with strange virtual address access

Hi Tom, I'm not sure. Again, I'd add the Vma and the SyscallVerbose debug flags which may help figure it out. It's possible that's the address of a dynamically-loaded library as well. Also, this trace looks like it came from Arm instead of x86. I don't have as much experience looking at Arm addre

[gem5-users] Re: Building Old gem5 error

Hello Abdelrahman, Unfortunately, it's incredibly difficult to keep the development environment for older versions of gem5 working. You may be able to find an old dockerfile in those gem5 repositories that could help to recreate the build environment. (I'm not sure if we were using docker at the t

[gem5-users] Re: Issue with strange virtual address access

Hi Liyan, This looks like a stack address to me, so it won't appear in the objdump. Since you're using SE mode, gem5 is controlling the physical address mappings (not the OS). You can use the "Vma" debug flag to see all of the virtual memory areas that gem5 creates/assigns. the "SyscallVerbose" f

[gem5-users] Re: How do I disable most statistics in the stats.txt under Atomic CPU

Hello, I don't believe there's a way to do that right now. However, in atomic mode, many stats *are* skipped as they are only accessed in the "timing" functions. I doubt it would make much performance difference. However, that's just a guess, and I could be wrong. Cheers, Jason On Wed, Mar 16, 2

[gem5-users] Re: Is thread lock not working under both SE and FS mode?

Hi Meng, It depends on the ISA you're using and the configuration of the system. For instance, x86+classic caches is known to have some synchronization issues. The transactional memory support only works with Arm, and I'm not sure which memory system it requires. What system are you trying to sim

[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

Hi Abdelrahman, > Is there a better way you can suggest using SPEC2017 in FS mode to > evaluate my system on gem5? > No, there's not a better way, as far as I know :). > My understanding is that the FS simulation is significantly slow. Any > guidelines on how to make it as fast as possible?

[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

Hi Abdelrahman, >From the get error message, it says: "This error may be caused by a too restrictive setting in the file '/proc/sys/kernel/perf_event_paranoid' The default value was changed to 2 in kernel 4.6 A value greater than 1 prevents gem5 from making the syscall to perf_event_open"

[gem5-users] Re: M5 Fs utility workbegin

inary in FS mode. > Note that I'm running first in KVM mode on a x86 host hoping to switch CPUs > once the work start event happens. Are magic ops unsupported in KVM mode? > > Thanks! > > > On Wednesday, March 9, 2022, 09:14:24 AM PST, Jason Lowe-Power via > gem5-users wrote

[gem5-users] Re: M5 Fs utility workbegin

Hi George, For workbegin/workend, they can be called from within applications if you link to the libm5 library. For instance, in the parsec resource here: https://resources.gem5.org/resources/parsec we use the m5_workbegin() function in the ROI hooks. See https://gem5.googlesource.com/public/gem5-

[gem5-users] Re: Inquiry on the gem5 communities and forums

Hi Jianda, There will also be a tutorial and workshop at ISCA in New York this year (June 11). More info coming soon! Cheers, Jason On Fri, Feb 18, 2022 at 8:21 AM Gabriel Busnot via gem5-users < gem5-users@gem5.org> wrote: > Hi and welcome Jianda, > > You are in the right place! Feel free to s

[gem5-users] Re: Not able to access webpage to run_npb.py

Hi David, Sorry for the confusion. We need to update that documentation! You can now find the script here: https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/configs/example/gem5_library/x86-npb-benchmarks.py (or in configs/example/gem5_library in the gem5 repo). Cheers, Jason On Thu,

[gem5-users] Re: Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3

Hello, This specific setup has not been tested, as far as I know. I would also suggest using v21.2.1 as there have been lots of bugfixes to CHI in the past year. Cheers, Jason On Tue, Feb 15, 2022 at 6:23 PM Liyichao via gem5-users wrote: > Hi All: > > Does the gem5 v21.0.1.0 support

[gem5-users] Re: Run srsRAN code with gem5

Hi Uma, Not all X86 vector instructions are implemented. What you're seeing is that pmovzxbw isn't implemented. Specifically, there's at least one version (as shown here https://www.felixcloutier.com/x86/pmovzx) which hasn't been implemented yet. I'm not sure which one. The `Vdq_Udq_or_Mq` somehow

[gem5-users] Re: findOrCreate function

Hi Scott, I think the answer is the same as the prior email. You need to register an exit callback to close the file stream :). See, for instance, the elastic trace code: https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/cpu/o3/probe/elastic_trace.cc#103 Cheers, Jason On Wed, Feb

[gem5-users] Re: Destructor for BaseCPU

Hi Scott, If you want something to execute before gem5 is completed, you can call `registerExitCallback`. See http://doxygen.gem5.org/release/current/namespacegem5.html#abcf3056836ee522620e5b14d9392ea87 I *think* that will solve your problem, but let me know if not. I don't think there's a clean

[gem5-users] Re: Problems on creating HelloObject & re-compiling following tutorial

Namespaces were recently added to gem5 and the documentation hasn't been updated, yet. We'll put that on the to do list. Cheers, Jason On Wed, Feb 2, 2022 at 6:11 AM Zhang Zhiyuan via gem5-users < gem5-users@gem5.org> wrote: > Dear gem5 faculties: > > Hi! I’ve been trying to follow the getting s

[gem5-users] Re: Clarification minor CPU “in-order”

Good question, Felix! The short answer is that since there are instructions that take multiple cycles to execute you need something like a scoreboard to track the dependencies. In the H&P book, you can see some details of this in Appendix C.5 (6th edition). If you happen to have the Patterson and

[gem5-users] Re: Compiling gem5 on ARM Based Host

Hi Sam, I was wondering when this problem would come up again. Here's a Jira issue to track the same thing in a different context: https://gem5.atlassian.net/browse/GEM5-1003 Could you do something like `du -h build/ | sort -h` to see what objects are the biggest? I'm going to guess that there ar

[gem5-users] Re: some problem about IO device's write or read function's return tick

Hello, If you are using *atomic* memory mode, then the tick number is mostly ignored. If you're using *timing* mode, then the tick number should be used by whatever object calls the read/write function and the delay is inserted there. Also, if your program doesn't have a direct dependence on the I

[gem5-users] Re: RISCV Full System with Ruby

Hi Fu, You can modify that file to import a Ruby-based cache hierarchy (e.g., MESI_Two_Level and MI_Example have been tested). Or, better yet, create your own run script. `riscv_fs.py` is just an *example* of how to use the standard library components. Cheers, Jason On Fri, Dec 24, 2021 at 7:57

[gem5-users] Re: Adding use of an external library

Hi Elliot, You may be able to get some inspiration from the code in gem5/ext/*. This is where we have included external libraries. Cheers, Jason On Fri, Dec 17, 2021 at 6:21 PM Eliot Moss via gem5-users < gem5-users@gem5.org> wrote: > > I have an external library that I would like to link with

[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode

Hi Brian, You can try the patch linked below if you want x86 + multicore + classic. There is a download button on that page. However, this isn't "officially" supported. Some Ruby protocols have been tested with x86 and multiple cores. The details on the gem5-resources website and/or repo should d

[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode

Hi Brian, A few quick thoughts: 1. x86 + classic cache + multicore is not supported. There is a changeset on gerrit (https://gem5-review.googlesource.com/c/public/gem5/+/52303) which may fix this, but it has not been tested widely. 2. SE mode + pthreads will likely not work in all circumstances. T

[gem5-users] Re: Run Timed Simulation (Stop After Certain Time)

You can call cpu.scheduleInstStop(, , ) So, you can set an initial instruction limit which will exit from the simulate() call. Then, you can reset the stats and set a new instruction limit with scheduleInstStop. Then, call simulate() again. When this second simulate returns you can dump the stats.

[gem5-users] Re: Run Timed Simulation (Stop After Certain Time)

Hi Abdelrahman, I think you have the right approach. Is the simulation not exiting after the warmup_inst instructions? Cheers, Jason On Sat, Dec 4, 2021 at 11:43 PM Abdelrahman S. Hussein via gem5-users < gem5-users@gem5.org> wrote: > Hello, > > I am trying to warm up my gem5 in order to train

[gem5-users] Re: fatal when adding a new CPU

Hi Fengze, Yeah, there's a lot of complicated and undocumented things you need to do when initializing a CPU. Here's a couple of pointers that may help. However, this code was written a few years ago and is almost 4000 commits behind, so things have probably changed since then! Code: https://gith

[gem5-users] Re: RISCV Full System with Ruby

Hello, Yes. MI_example and MESI_Two_Level have been tested with the RISC-V board in the components library. See https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/components-library/riscv_fs.py I am working on the CHI protocol. I have a WIP changeset that I could share

[gem5-users] Re: m5 pesudo

Hello, The m5 magic operations (either via magic instructions or addresses) will work with all CPU models. Cheers, Jason On Sat, Oct 30, 2021 at 8:31 PM Liyichao via gem5-users wrote: > Hi All: > > Does “m5 --addr 0x1001 exit” take effect in the O3 system? > > > __

[gem5-users] Re: Vector Instructions Support

Hi Nitesh, I don't think there's any good documentation. This may help with Arm SVE support, but it's from a while ago. Things have changed since 2018. https://community.arm.com/arm-research/b/articles/posts/simulating-the-arm-sve-with-gem5 On Fri, Oct 29, 2021 at 2:27 AM Nitesh Narayana GS wrot

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