Micron Confidential
Does gem5 support having multiple cache line sizes (e.g. a non-coherent cache,
below the point of coherence, having a larger line size)?
Regards,
Patrick
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To
Does anyone know if there exists a generic DMA engine that allows automated
transfer of data from one memory range to another?
In dma_device.hh, there's DmaDevice, which looks like it provides a foundation,
and there's DmaReadFifo which provides a good example, but stores the data
internally
Micron Confidential
I am trying to replay an elastic trace taken with an X86 system (built
similarly as in fs.py - using common.FSConfig.makeLinuxX86System).
However, when I try to replay the trace, using the same system, but switching
to the TraceCPU, I get the following assertion error:
handle. Instead of calling map_m5_mem, you'd need to set up a
virtual to physical mapping for the magic address on your own somehow, and then
set the m5_mem pointer to whatever virtual address it should use.
Gabe
On Wed, Nov 4, 2020 at 3:00 PM Patrick Sheridan (psheridan) via gem5-users
mailto:gem5
Micron Confidential
I was wondering if it is possible to use m5ops (e.g. m5_exit(0)) while using
the X86KvmCPU. Currently, when I hit this instruction, rather than exiting,
the kernel panics with the message below. If this is not possible, is there a
workaround to use the X86KvmCPU to
