Hi,
I'm trying to write an application and run it on multiple ARM cores. Here's the
problem:
If I have M5EXIT at the end of application, the first core to complete will end
gem5 execution.
1 way to solve:
I want to create a distinct gem5 Event from every core and push it to gem5
EventQueue at
Hi Andreas,
Yes, I do have them in my PATH preceding system installation. But, the error
remains.
Thanks,
Uday
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Andreas Hansson
Sent: Friday, November 15, 2013 2:06 PM
To: gem5 users mailing list
Subject: Re: [g
Hi,
I'm trying to build ARM in gem5 version r9978.
Scons complains of not finding Python.h because py_includes in SConstruct
doesn't find my Python2.7.3 (non-default installation) although I've set
PYTHONHOME, PYTHONLIB & PYTHONPATH.
I didn't face this issue in previous gem5 versions. So, has a
Hi all,
I'm planning to start using SLICC infrastructure that gem5 provides. I'm very
new to the whole Ruby system though!
Can anyone please answer these questions:
1.How do I start using SLICC?
2.How do I generate c++ classes in MI_example?
3.Do I necessarily need to build a gem
Hi all,
I'm planning to start using SLICC infrastructure that gem5 provides. I'm very
new to the whole Ruby system though!
Can anyone please answer these questions:
1.How do I generate c++ classes in MI_example?
2.Do I necessarily need to build a gem5 + Ruby Memory System to realize a
Hi all,
I'm planning to start using SLICC infrastructure that gem5 provides. I'm very
new to the whole Ruby system though!
Can anyone please answer these questions:
1.How do I generate c++ classes in MI_example?
2.Do I necessarily need to build a gem5 + Ruby Memory System to realize a
: Ranga, L Udaya
Cc: gem5 users mailing list
Subject: RE: [gem5-users] Cache an address in ARM System
Hi Uday,
Assuming you're using linux, most memory should be marked as cached. It really
depends on what memory you're talking about and who is using it. Assuming linux
when memory is
Ali,
How do I edit/configure page table as cached or otherwise?
Thanks,
Uday
-Uday
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Ranga, L Udaya
Sent: Friday, July 12, 2013 9:34 AM
To: sa...@umich.edu; gem5 users mailing list
Subject: Re: [gem5-users
-Original Message-
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Ranga, L Udaya
Sent: Friday, July 12, 2013 2:42 PM
To: gem5 users mailing list
Subject: Re: [gem5-users] MemCmd for CleanInvalid
Hi Andreas,
I have used Invalidate and memWriteBack in
t sends an atomic or timing request (the request type
depends on the current memory mode) to the next level in the memory hierarchy.
//Andreas
On 07/02/2013 01:18 PM, Ranga, L Udaya wrote:
>
> Hi Ali,
>
> Can you please help me identify the code that drains a cache?
>
> At check
) to be guaranteed?
Code in cache_impl.hh seem to suggest otherwise. Seems like
pkt->memInhibitAsserted() is what I need to check.
Is my understanding correct?s
-Uday
From: gem5-users-boun...@gem5.org<mailto:gem5-users-boun...@gem5.org>
[mailto:gem5-users-boun...@gem5.org] On Be
is what I need to check.
Is my understanding correct?s
-Uday
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Ranga, L Udaya
Sent: Wednesday, July 10, 2013 3:06 PM
To: gem5 users mailing list
Subject: [gem5-users] handleSnoop semantics
Hi all,
Assume that a sn
-users] Cache an address in ARM System
Assuming the page table maps the address as cacheable it should just happen. Do
you mean the line needs to be locked in the cache?
Ali
On 10.07.2013 06:25, Ranga, L Udaya wrote:
Hi all,
I need to ensure that a particular address is cached by ARM’s L1
Hi all,
I need to ensure that a particular address is cached by ARM's L1/L2 cache.
Can anyone please tell me how I can do it?
Thanks,
Uday
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Hi all,
Assume that a snoop master calls sendTimingSnoopReq( Pkt ) which results to:
Cache::recvTimingSnoopReq(), which tries to find a block BlkType*
blk) for given packet address. It then passes on blk to handleSnoop() which
simply returns back for an invalid block.
How should the snoop master
the memory hierarchy.
//Andreas
On 07/02/2013 01:18 PM, Ranga, L Udaya wrote:
>
> Hi Ali,
>
> Can you please help me identify the code that drains a cache?
>
> At checkpoint function (serialize()) in cache_impl.hh, there is a
> warning message to drain the cac
support for doing it for checkpointing, but there isn't a way to
do it without checkpoint. If you want to do this you'd need to add the
functionality.
Ali
On Jun 25, 2013, at 11:26 PM, "Ranga, L Udaya"
mailto:udayara...@ti.com>> wrote:
Hi Ali,
Is there a way to flu
support for doing it for checkpointing, but there isn't a way to
do it without checkpoint. If you want to do this you'd need to add the
functionality.
Ali
On Jun 25, 2013, at 11:26 PM, "Ranga, L Udaya"
mailto:udayara...@ti.com>> wrote:
Hi Ali,
Is there a way to flu
un 25, 2013, at 4:25 AM, "Ranga, L Udaya"
mailto:udayara...@ti.com>> wrote:
Hi,
I found MemCmd::FlushReq and MemCmd::InvalidationReq in gem5 MemCmd enum. How
do I convey CleanInvalid command, whose definition is “cache clean and
invalidate operation”? is there a way to place m
Hi,
In recvTimingSnoopResp(PacketPtr pkt ), is pkt->hasData() OR
pkt->memInhibitAsserted() the correct API to know whether any master gave snoop
data (snoop hit/miss)?
Thanks,
Uday
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-b
Hi,
I found MemCmd::FlushReq and MemCmd::InvalidationReq in gem5 MemCmd enum. How
do I convey CleanInvalid command, whose definition is "cache clean and
invalidate operation"? is there a way to place multiple commands in a single
packet?
Thanks,
Uday
__
Thanks Andreas,
I could get a unique masterID from the system by providing a string.
-Uday
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Andreas Hansson
Sent: Monday, June 24, 2013 5:28 PM
To: gem5 users mailing list
Subject: Re: [gem5-users] masterID for s
Hi Andreas,
What you say is true for an interconnect-like module that uses a "normal"
request to create a "snoop" request.
But, in my case, I have to create a snoop request from scratch because this
snoop request originally is from an interconnect-like module in a different bus
protocol domain
Hi,
I have a module (derived from SimpleMemory) which has an instance of type
'SlavePort'. I need to call sendTimingSnoopReq( PacketPtr ) on this port. For
this I have to first create a Request and then Packet.
Request() constructor needs a mastered. I understand that typically this is
obtaine
Hi,
I have a topology as follows:
ARM_CPU <-> L1_Data_Cache <-> L2_Coherent_Bus <-> L2_Cache <->
Memory_Coherent_Bus <-> My_Bridge
My_Bridge has a SimpleMemory to connect with Memory_Coherent_Bus.
If My_Bridge has to snoop into ARM_CPU, are these assumptions correct for a
Snoop Read transacti
Hi,
I get a lot of error messages while building gem5 which are related to
uninitialized warnings being treated as errors. I tried adding specific flags
for compiler to ignore this fact, but couldn't get past this check. Is there a
single point in SConstruct(s), where I can force this behavior.
Hi,
Can anyone please clarify why alarm(1) is coded in gem5/src/base/pollevent.cc
(line 246)?
In my simulation framework, this causes the simulation to advance slightly. I
need to know whether this call is essential or I can bypass it.
Thanks,
Uday
Ok I figured the source of error to be the value of __SUNPRO_CC?
What should this value be?
-Uday
From: Ranga, L Udaya
Sent: Wednesday, April 03, 2013 1:07 PM
To: 'gem5 users mailing list'
Subject: SWIGTEMPLATEDISAMBIGUATOR error
Hi,
When I build gem5 with gcc4.7.2 compiler, I get
Hi,
When I build gem5 with gcc4.7.2 compiler, I get this error:
sysc_build/ARM/python/swig/stats_wrap.cc:16137:40: error: 'template' (as a
disambiguator) is only allowed within templates
Any reason why this happens?
Attahced is the complete error log.
Thanks,
Uday
sysc_build.log
Description
? Are you including libprotobuf in the process?
Andreas
From: , L Udaya mailto:udayara...@ti.com>>
Reply-To: gem5 users mailing list
mailto:gem5-users@gem5.org>>
Date: Thursday, 28 March 2013 04:41
To: "Ranga, L Udaya" mailto:udayara...@ti.com>>, gem5 users
mailing lis
Andreas,
Is there a way I can disable usage of protoc?
I'm using RHEL machine, so one thing I can try is to install protobuf-devel
package too.
-Uday
From: Ranga, L Udaya
Sent: Wednesday, March 27, 2013 11:29 AM
To: 'gem5 users mailing list'
Subject: RE: [gem5-users] protoc
Hi Andreas,
Yeah, I compiled and ran gem5.opt w/ hello_world successfully.
But, .so still complains of the undefined symbol
_ZNK6google8protobuf7Message11GetTypeNameEv.
-Uday
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Andreas Hansson
Sent: Tuesday, Mar
Hi,
I get the following error upon trying to build gem5:
Warning: Protocol buffer compiler (protoc) not found.
Please install protobuf-compiler for tracing support.
I have compiled and installed protobuf, how do I indicate it to gem5 build
system?
I have tried:
1. Setting environment PR
try setting LIBRARY_PATH as well.
Ali
On Feb 11, 2013, at 3:16 AM, "Ranga, L Udaya" wrote:
> Ok, the scons_config.log complains that /usr/bin/ld connot find -lpython2.7.
>
> I have in my LD_LIBRARY_PATH and PYTHONLIB environment
> variables. How can I force gem5's S
to do when it ran CheckLib and failed (It does so by
attempting to link a program with the library, so you should see meaningful
output about which library caused a problem.)
Ali
On 2/5/13 12:39 PM, "Ranga, L Udaya" wrote:
>Hi Ali,
>
>I have tried this approach and it did
you probably want to call python2.7 .
Thanks,
Ali
On 2/2/13 11:11 PM, "Ranga, L Udaya" wrote:
>Ali,
>
>I'm using Linux x86_64 - RHEL4 and have configured python2.7 with
>--enable-shared option. My LD_LIBRARY_PATH points to libpython2.7.so.
>
>-Original Me
.
See http://www.gem5.org/Using_a_non-default_Python_installation for more
information.
Ali
From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] On Behalf Of
Ranga, L Udaya [udayara...@ti.com]
Sent: Saturday, February 02, 2013 12:16 AM
To: gem5 users ma
Hi all,
I'm trying to build gem5 with Python 2.7.3 and gcc4.7.2.
Below is the error message with which scons terminates.
Can you please tell me how to build C library for Python2.7?
Checking for C library pthread... (cached) yes
Checking for C library dl... (cached) yes
Checking for C library u
Hi,
I am trying to build ARM simulator on Gem5 using "scons build/ARM/gem5.opt".
Compilation goes through and link fails. Here are the first few lines of build:
undefined reference to `Py_SetProgramName'
undefined reference to `Py_Initialize'
undefined reference to `Py_Finalize'
undefined refere
Hi,
I have been trying to successfully run a simulation on GEM5 and am blocked by
many issues I faced while building a model.
Upon reading documentation, I am using these tools and still am getting errors
like "Python.h not found, pthread not found, can't open libmpfr.so.1 " etc.
Below are det
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