[gem5-users] McPat power results with/without ECC protection

Hello, I have a couple of questions regarding McPat. I have a single core system with two different configuration with/without ECC support on L1 cache. I run the same workload on two different schemes, however the power consumption values taken from McPat are interesting. Values taken

Re: [gem5-users] McPat power results with/without ECC protection

). I would argue that any number that comes out of McPat should be considered dubious at best. There are far more efficient ways to generate pseudo-random numbers... Andreas On 26/08/2015 09:10, gem5-users on behalf of Sanem Arslan gem5-users-boun...@gem5.org on behalf of sanem.ars...@boun.edu.tr

Re: [gem5-users] PARSEC outputs for ALPHA FS mode

[HOOKS] Terminating Done :D *sync: applet not found* On Thu, Mar 19, 2015 at 3:12 AM, Sanem Arslan sanem.ars...@boun.edu.tr wrote: Hi Vinayak, I have used busybox sync command before exiting the simulation to write all changes to disk. For example: ./blackscholes 1 /parsec/install/inputs

Re: [gem5-users] PARSEC outputs for ALPHA FS mode

Hi Vinayak, I have used busybox sync command before exiting the simulation to write all changes to disk. For example: ./blackscholes 1 /parsec/install/inputs/blackscholes/in_4K.txt /parsec/install/inputs/blackscholes/prices.txt echo Done :D busybox sync /sbin/m5 exit Bests, Sanem

Re: [gem5-users] how to update m5struct in vmlinux_2.6.27-gcc_4.3.4

gem5-users gem5-users@gem5.org These patches will give an idea, and they're not difficult to port. http://repo.gem5.org/linux-patches/ Anthony Gutierrez http://web.eecs.umich.edu/~atgutier On Thu, Nov 6, 2014 at 3:38 PM, Sanem Arslan via gem5-users gem5-users@gem5.org wrote: Hello, I want

Re: [gem5-users] how to update m5struct in vmlinux_2.6.27-gcc_4.3.4

gem5-users gem5-users@gem5.org These patches will give an idea, and they're not difficult to port. http://repo.gem5.org/linux-patches/ Anthony Gutierrez http://web.eecs.umich.edu/~atgutier On Thu, Nov 6, 2014 at 3:38 PM, Sanem Arslan via gem5-users gem5-users@gem5.org wrote: Hello, I want

[gem5-users] how to update m5struct in vmlinux_2.6.27-gcc_4.3.4

Hello, I want to update m5struct.c to take additional information from the kernel. I am using kernel, PAL code and disk image for the ALPHA provided by UT Texas (http://www.cs.utexas.edu/~parsec_m5/). In order to update m5struct, I should reach to files inside vmlinux_2.6.27-gcc_4.3.4

Re: [gem5-users] thread migration

Hi Steve, First of all thank you very much for your response. I will do thread migration multiple times and this method has performance overhead due to high drain cycles. AFAIK, this method is to migrate hardware threads. Actually, I want to migrate software threads rather than hardware

Re: [gem5-users] gem5 cache latency, impact on performance

() somewhere in the code that never executes! Can you confirm that by breakpoints? On 4/4/14, Sanem Arslan sanem.ars...@boun.edu.tr wrote: Hi all, I am using classic memory system and I have added several codes to the cache_impl.hh and blk.hh files. However I cannot see the performance overhead

Re: [gem5-users] gem5 cache latency, impact on performance

. De: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] en nombre de Mahmood Naderan [mahmood...@gmail.com] Enviado: sábado, 05 de abril de 2014 19:48 Para: Sanem Arslan CC: gem5 users mailing list Asunto: Re: [gem5-users] gem5 cache latency, impact on performance

[gem5-users] gem5 cache latency, impact on performance

Hi all, I am using classic memory system and I have added several codes to the cache_impl.hh and blk.hh files. However I cannot see the performance overhead of these added codes on the gem5 execution time. I have increased cache latency parameters from CacheConfig.py file and I can see

[gem5-users] fault injection to dcache

Hello All, I want to inject faults (bit flip model) into the data cache during the application execution. I plan to generate three random numbers to select which cache line, which bit of the data within the cache line and which clock cycle that the fault will be injected. However I do

[gem5-users] cache, access, handleFill, satisfyCpuSideRequest, memcpy

Hi, I want to trace cache data where it is read from or written in caches blocks. There are several methods in cache_impl.hh file like access, handleFill and satisfyCpuSideRequest. In access and handleFill methods, a cache block is written like that: std::memcpy(blk-data,

Re: [gem5-users] Problem about Create Checkpoint

Hi all, I have some problems about creating checkpoint. I want to take the checkpoint from the source code (queens.c). I have added #include “util/m5/m5op.h” into the source code and I put m5_checkpoint(0,0) and m5_dumpreset_stats(0,0) statements at the ROI (as shown in gem5 hipeac 2012

Re: [gem5-users] Panic: initiateAcc not defined! error with ruby_fs.py on x86

about these errors? Thank you in advance for your time and help. Best Regards, Sanem Sanem Arslan sanem.ars...@boun.edu.tr Hi all, I encounter the error as following when I simulate ruby_fs.py on x86. 1. scons build/X86/gem5.opt PROTOCOL=MESI_CMP_directory RUBY=True 2. build/X86/gem5.opt

[gem5-users] Panic: initiateAcc not defined! error with ruby_fs.py on x86

Hi all, I encounter the error as following when I simulate ruby_fs.py on x86. 1. scons build/X86/gem5.opt PROTOCOL=MESI_CMP_directory RUBY=True 2. build/X86/gem5.opt configs/example/ruby_fs.py --disk-image=/home/sanem/full_system_images/disks/linux-x86.img

[gem5-users] cache protection in gem5

Hi all, I have a question about cache protection. I want to apply parity or ECC on L1/L2 caches. Should I enable or disable ECC on cache structures in gem5? Or by default, there is no protection on caches. Which files should I modify? By the way, I am using X86 with full system mode.