as
>
> From: Erfan Azarkhish
> Reply-To: gem5 users mailing list
> Date: Monday, 4 May 2015 14:29
> To: gem5 users
> Subject: [gem5-users] Cache Flushing in FS-ARM
>
> Dear All,
>
> I am running a full-system ARM simulation
> (aarch-system-2014-10/vmlinux.aarch
ers@gem5.org>>
Subject: [gem5-users] Cache Flushing in FS-ARM
Dear All,
I am running a full-system ARM simulation
(aarch-system-2014-10/vmlinux.aarch32.ll_20131205.0-gem5).
I intend to flush the L1 and L2 caches in my device driver.
For the L1 cache, I succeed without any problem, but for the L2
Dear All,
I am running a full-system ARM simulation
(aarch-system-2014-10/vmlinux.aarch32.ll_20131205.0-gem5).
I intend to flush the L1 and L2 caches in my device driver.
For the L1 cache, I succeed without any problem, but for the L2 cache when
I use *outer_clean_range()*, nothing happens, and w
