(There was a typo in previous mail)
Hello Nikos and Everyone,
In src/mem/cache/cache.cc for function handleTimingReqMiss(), we only check
if there is an existing mshr entry corresponding to Miss Request. And then
we call *BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time,
Hello Nikos and Everyone,
In src/mem/cache/cache.cc for function handleTimingReqMiss(), we only check
if there is an existing mshr entry corresponding to Miss Request. And then
we call *BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time,
request_time);*
In
I want to have just 1 target per cache line in MHSR queue ie., one target
per MSHR entry, but if I set parameter tgt_per_mshr to be 1, I get the
number of blocked cycles to zero i.e, there is no blocking due to full
targets.
If we see the allocateMissBuffer calls code in base.cc and base.hh, the
Hi Abishek,
A single MSHR can keep track of more than one requests for a given cache
line. If you set tgts_per_mshr to 1, then the MSHR will only be able to
keep track of a single request for any given cache line. But it can
still service requests to other cache lines by allocating more MSHRs.
Hello Everyone,
I am trying to simulate D-cache with one target per mshr, I tried changing
the parameter "tgts_per_mshr" defined in "configs/common/Caches.py" to 1,
it does not work.
This is because when we allocate target for existing MSHR, we always check
the "tgts_per_mshr" parameter after
