Dear, everyone.
I try to full system simulation for ARM ISA.
So, I downloaded the pre-compiled kernels and disk images
(aarch-system-20170616.tar.xz) from the repository (
http://www.gem5.org/dist/current/arm/).
There are several dtb files like below.
vexpress-v2p-ca15-tc1-gem5_1cpus.20170616.dtb
Yes, if you don't modify the dtb, the Linux kernel won't see the
change in the number of CPUs change, this can be verified with cat
/proc/cpuinfo.
You can modify the dtb directly by first converting it to dts human
readable form:
https://stackoverflow.com/questions/14000736/tool-to-visualize-the-
Ah, nevermind, I had forgotten this, the dtbs are tracked inside the gem5 tree:
https://github.com/gem5/gem5/blob/a66fe6a8c36c9ab49cb3a35065bfc645d51036c8/system/arm/dt/armv8.dts
an built with:
make -C system/arm/dt
The Makefile uses the cpp preprocessor to generate the dtbs with
different core
Thanks a lot.
It is great helpful to me.
2018-03-06 22:17 GMT+09:00 Ciro Santilli :
> Ah, nevermind, I had forgotten this, the dtbs are tracked inside the gem5
> tree:
>
> https://github.com/gem5/gem5/blob/a66fe6a8c36c9ab49cb3a35065bfc6
> 45d51036c8/system/arm/dt/armv8.dts
>
> an built with:
>
>
New versions of gem5 also auto-generate DTBs. This requires support from the
simulation script, but that should already be implemented for the
configurations in configs/example/arm/ and fs.py. The latter might requires
that --generate-dtb is specified to enable this. Keep in mind that the
gene
Hello Andreas,Haeyoon Cho,
Andreas , thanks thi worked for me too. fs simulation on Arm with 16 CPUS.
I wanted to know if any one of you have tried GARNET on ARM?
Inputs would really be helpful.
I want to simulate a 4*4 mesh garnet system on ARM
Thank you in advance.
Regards,
Sahana Prasad
On
