On 8/14/2023 3:47 PM, Khan Shaikhul Hadi wrote:
Instead of directly connecting all level 1 caches ( icache, dcache etc) to CPU and next level bus, I
want to create a controller module that will have all those caches . This controller module will
receive all cpu requests and distribute them to
On 8/14/2023 1:42 PM, Khan Shaikhul Hadi wrote:
Initially I was thinking doing something like this as you suggested:
CpuSidePort cacheMemSidePortConnection = cache.memSidePort;
MemSidePort cacheCpuSidePortConnection = cache.cpuSidePort;
problem is when I looked into how python code
On 8/14/2023 11:58 AM, Khan Shaikhul Hadi via gem5-users wrote:
In my code I'll have a simobject which has its own cache. As classical cache use CpuSidePort and
MemSidePort to receive and respond to request, I want to create some internal CpuSidePort and
MemSidePort in my simobject like below
